EDA 實作 Verilog Tutorial 國研院國家晶片系統設計中心 July 2005 陳正斌

Traditional VLSI Design Flow

EDA Electronic Design Automation (EDA) Computer-Aided Design (CAD)

Hardware Description Language A hardware description language (HDL) is a high- level programming language with special constructs used to model the function of hardware logic circuits. The special language constructs can: –Describe the connectivity of the circuit –Describe the functionality of the circuit –Describe the timing of a circuit

Verilog Verilog is a Hardware Description Language. Verilog models digital circuits. Verilog lets you develop tests to verify the functionality of the circuits you model.

Verilog Module

Module Ports

Module Instances

A Simple and Complete Example

Sample Design – Full Adder x in y in c in coutsum

Full Adder – Boolean Algebra cout = x in y in c in ’+ x in y in c in +x in ’y in c in +x in y in ’c in = x in y in +c in (x in ’y in +x in y in ’) = x in y in + c in (x in ⊕ y in ) sum = x in ’y in ’c in + x in ’y in c in ’+x in y in ’c in ’+x in y in c in = (x in ’y in +x in y in ’)c in ’ + (x in ’y in ’+x in y in ) c in = (x in ⊕ y in ) ⊕ c in

Full Adder – Schematic

Full Adder – Verilog Model module COUT(cout, xin, yin, cin); input xin; input yin; input cin; output cout; wire xin, yin, cin, out; wire p1, p2, p3; and (p1, xin, yin); xor (p2, xin, yin); and (p3, p2, cin); or (cout, p1, p3); endmodule module SUM(sum, xin, yin, cin); input xin; input yin; input cin; output sum; xor (sum, xin, yin, cin); endmodule

Full Adder -- Schematic

Full Adder – Verilog Model module FA(Cii,Si,Xi,Yi,Ci); input Xi; input Yi; input Ci; output Cii; output Si; SUM inst0 (.sum(Si),.xin(Xi),.yin(Yi),.cin(Ci)); COUT inst1 (.cout(Cii),.xin(Xi),.yin(Yi),.cin(Ci)); endmodule

Test Bench -- Template module FA_test; //Signal declaration //Instantiate modules //Apply stimulus //Display results endmodule

Test Bench --Instance module FA_test; //Signal declaration //Instantiate modules FA inst0 (Cii,Si,Xi,Yi,Ci); //Apply stimulus //Display results endmodule

Test Bench -- Stimulus module FA_test; // Signal declaration reg Xi, Yi, Ci; // Instantiate modules FA inst0 (Cii,Si,Xi,Yi,Ci); // Apply Stimulus initial begin #0 Xi = 0; Yi = 0; Ci = 0; #10 Xi = 0; Yi = 0; Ci = 1; #10 Xi = 0; Yi = 1; Ci = 0; #10 Xi = 0; Yi = 1; Ci = 1; #10 $finish; end //Display results endmodule TimeValues XiYiCi

Test Bench – Display Result module FA_test; // Signal declaration reg Xi, Yi, Ci; // Instantiate modules FA inst0 (Cii,Si,Xi,Yi,Ci); // Apply Stimulus initial begin #10 Xi = 0; Yi = 0; Ci = 0; #10 Xi = 0; Yi = 0; Ci = 1; #10 Xi = 0; Yi = 1; Ci = 0; #10 Xi = 0; Yi = 1; Ci = 1; #10 $finish; end //Display results initial // print all changes to all signal values $monitor($time, " Xi = %b Yi = %b Ci = %b Ci+1 = %b Si = %b", Xi,Yi,Ci,Cii,Si); endmodule

Dump Waveform initial begin $dumpfile(“file.vcd”); $dumpvars(0,inst0); end

Simulation unix> verilog FA_test.v FA.v COUT.v SUM.v unix> nWave &

Waveform

Quiz Design a 4 bit adder by instancing 4 full adder

Edit ADDR4.v module ADDR4(cout,sum,a,b,cin); input cin; input [3:0] a; input [3:0] b; output [3:0] sum; output cout; //Design Started Here!!! endmodule

Apply Stimulus Edit ADDR4_test.v // Apply Stimulus initial begin // ** Add stimulus here ** end

Apply Stimulus TimeValues abCin