Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI System Design Lecture 12 - Timing, Project Overview
3/10/03Lecture 12 - Timing, Proj. Overview 2 Announcements Exam 1 - Take-Home Out: March 24 Due: March 31 Timing References Synopys Online Documentation (SOLD) Manuals - access using the "sold" command: Design Compiler User Guide Design Compiler Tutorial Design Compiler Reference Manual Pran Kurup and Taher Abbasi, Logic Synthesis using Sysnopsys®, 2nd ed., Kluwer Academic Publishers, 1997.
3/10/03Lecture 12 - Timing, Proj. Overview 3 Where we are... Last Time State Coding & Assignment Timing Today Timing in Synopsys Tools Project Overview
3/10/03Lecture 12 - Timing, Proj. Overview 4 Timing in the Design Compiler DC assumes a synchronous, clock-based system Derives setup, hold constraints between registers User-specified timing constraints on inputs, outputs DQ DQ DQ DQ Comb. Logic (Internal) Comb. Logic (Output) Comb. Logic (Input) Register-Register Timing Paths Input Timing Paths Output Timing Paths
3/10/03Lecture 12 - Timing, Proj. Overview 5 Specifying Timing in Synopsys DC Clock specification (See last lecture slide 37-38) Period Skew (and uncertainty) Input constraints Output constraints Combinational delay constraints Special cases false paths multicycle paths
3/10/03Lecture 12 - Timing, Proj. Overview 6 Input Constraints: A Closer Look Rationale: assume input is tied to some "other" module input delay = output delay of other module Example: set_input_delay 17 -clock clk d1 d1 17 ns clk 17 ns d1 comb. logic D Q comb. logic "current design" module clk comb. logic D Q "other" module
3/10/03Lecture 12 - Timing, Proj. Overview 7 Input Constraints: A Closer Look Impacts delay of input logic (of current design) Creates maximum timing constraint for setup time Creates minimum timing constraint for hold time d1 17 ns clk comb. logic D Q "other" module d1 input logic D Q comb. logic "current design" module 17 ns t ci t su
3/10/03Lecture 12 - Timing, Proj. Overview 8 Output Constraints: A Closer Look Rationale: assume output is tied to some "other" module output delay = input delay of other module + setup time Example: set_output_delay 5 -clock clk d1 d2 5 ns clk d2 comb. logic D Q output logic "current design" module 15 ns comb. logic D Q "other" module
3/10/03Lecture 12 - Timing, Proj. Overview 9 Output Constraints: A Closer Look Impacts delay of output logic (of current design) Creates maximum timing constraint for setup time Creates minimum timing constraint for hold time d2 5 ns clk comb. logic comb. logic D Q D Q output logic "current design" module "other" module clk 15 ns t co t pff
3/10/03Lecture 12 - Timing, Proj. Overview 10 Timing Constraints Example VHDL Code: library ieee; use ieee.std_logic_1164.all; entity timing_ex is port( a, b, clk, reset : in std_logic; d : out std_logic ); end; architecture behavior of timing_ex is signal f : std_logic; begin process (clk, reset) begin if (reset = '0') then f <= '0'; elsif (rising_edge(clk)) then f <= a; end if; end process; process (clk, reset) begin if (reset = '0') then d<='0'; elsif (rising_edge(clk)) then d <= f and b; end if; end process; end;
3/10/03Lecture 12 - Timing, Proj. Overview 11 Timing Constraints Example Timing Constraints: create_clock clk -period 10.0 set_fix_hold clk /* check hold time */ set_input_delay 0.5 -clock clk {a,b} set_output_delay 1.0 -clock clk d ; Synthesized Design:
3/10/03Lecture 12 - Timing, Proj. Overview 12 Getting Timing Reports: Seeing timing results: report_timing command report_timing -max_paths 5 Result: **************************************** Report : timing -path full -delay max -max_paths 5 Design : timing_ex Version: Date : Thu Apr 5 15:26: **************************************** Operating Conditions: Wire Load Model Mode: top (continued)
3/10/03Lecture 12 - Timing, Proj. Overview 13 Timing Report - Register to Register Startpoint: f_reg (falling edge-triggered flip-flop clocked by clk') Endpoint: d_reg (falling edge-triggered flip-flop clocked by clk') Path Group: clk Path Type: max Point Incr Path clock clk' (fall edge) clock network delay (ideal) f_reg/CLK2 (dfrf301) f f_reg/Q (dfrf301) f U32/O2 (nanf211) f d_reg/DATA1 (dfrf301) f data arrival time 1.33 clock clk' (fall edge) clock network delay (ideal) d_reg/CLK2 (dfrf301) f library setup time data required time data required time 9.74 data arrival time slack (MET) 8.41
3/10/03Lecture 12 - Timing, Proj. Overview 14 Timing Report - Output Logic Startpoint: d_reg (falling edge-triggered flip-flop clocked by clk') Endpoint: d (output port clocked by clk) Path Group: clk Path Type: max Point Incr Path clock clk' (fall edge) clock network delay (ideal) d_reg/CLK2 (dfrf301) f d_reg/Q (dfrf301) f d (out) f data arrival time 0.97 clock clk (rise edge) clock network delay (ideal) output external delay data required time data required time 9.00 data arrival time slack (MET) 8.03
3/10/03Lecture 12 - Timing, Proj. Overview 15 Timing Report - Input Logic Startpoint: a (input port clocked by clk) Endpoint: f_reg (falling edge-triggered flip-flop clocked by clk') Path Group: clk Path Type: max Point Incr Path clock clk (rise edge) clock network delay (ideal) input external delay f a (in) f f_reg/DATA1 (dfrf301) f data arrival time 0.50 clock clk' (fall edge) clock network delay (ideal) f_reg/CLK2 (dfrf301) f library setup time data required time data required time 9.77 data arrival time slack (MET) 9.27
3/10/03Lecture 12 - Timing, Proj. Overview 16 Other Timing Constraint Functions Tell timing analyzer to ignore a false path set_false_path -from source -to dest Specify combinational delays set_min_delay amt -from source -to dest set_max_delay amt -from source -to dest Specify multicycle path of N cycles set_multicylce_path N -from source -to dest
3/10/03Lecture 12 - Timing, Proj. Overview 17 How DC Works With Constraints Compile (Optimization) Steps Initial mapping to gates in library Delay optimization: attempt to fix constraint violations Design rule fixing: attempt to fix design rule violations Area optimization: attempt to meet area constraints without creating timing violations What happens when DC can't meet constraints Apply flattening (if you can afford to) Re-work constraints
3/10/03Lecture 12 - Timing, Proj. Overview 18 Using DC With Large Designs DC can't optimize large designs as one unit Typical approach: use hierarchy to control Control runtime Control optimization strategy
3/10/03Lecture 12 - Timing, Proj. Overview 19 Using DC With Large Designs (cont'd) Compilation strategies Top-down - compile all submodules together Bottom-up - compile leaf modules first, then move up (use "characterize" commands to get input, output delays) Mixed - use different approaches as appropriate in different levels of hierarchy
3/10/03Lecture 12 - Timing, Proj. Overview 20 Synthesize Blocks / Timing Analysis Timing OK? Place & Route / Timing Analysis Timing OK? N N Y Y DONE START Design Compiler Circuit extraction provides accurate timing; "Back Annotation"identifies critical paths Timing in Design Flow - ASIC Design
3/10/03Lecture 12 - Timing, Proj. Overview 21 Project Overview - WimpNet03 Key idea: computers communicate on shared wires (ether) Each computer has 8-bit address Information passed as packets
3/10/03Lecture 12 - Timing, Proj. Overview 22 Packet Format Header destination address (8 bits) source address (8 bits) length (8 bits) Data - up to 255 bytes CRC Byte - Error Code All bytes transmitted with LSB first
3/10/03Lecture 12 - Timing, Proj. Overview 23 Control Procedure - CSMA/CD CSMA/CD Carrier Sense Multiple Access with Collision Detection Procedure Defer - don’t transmit when carrier sense Transmit - transmit while monitoring data Collision - error in transmission when two stations transmit at same time Abort - terminate transmission and jam 4-6 bytes Backoff - wait for a random retransmission delay Retransmit - try again after backoff
3/10/03Lecture 12 - Timing, Proj. Overview 24 Project Goals Build a complete WimpNet03 Interface Chip Receiver with buffer RAM Transmitter with buffer RAM Area budget: 4 MOSIS Tiny Chips (4400 X 4400 )
3/10/03Lecture 12 - Timing, Proj. Overview 25 Transmitter Details
3/10/03Lecture 12 - Timing, Proj. Overview 26 Receiver Details
3/10/03Lecture 12 - Timing, Proj. Overview 27 RAM Subsystem Details Two-port organization Write port - writes on falling edge of clk when w_en_l =L Read port Size: 256 Bytes
3/10/03Lecture 12 - Timing, Proj. Overview 28 Design Groups Receiver Design Transmitter Design RAM Subsystem Design Chip assembly
3/10/03Lecture 12 - Timing, Proj. Overview 29 Coming Up More about the Project Subsystem Design: RAM