Project Characterization Real Time Image Processing Presented by: Baruch Koren Shahaf Fisher Technion – Israel Institute Of Technology Electrical Engineering Department Instructor: Mr. Almog Assaf

Project’s Goals Preparing a systematic infrastructure for future laboratories projects. Preparing instructions for integrating new components to this system. Preparing a systematic infrastructure for future laboratories projects. Preparing instructions for integrating new components to this system. Studying this complex system: the environment and the designing tools. Studying this complex system: the environment and the designing tools. Studying VHDL language, with an emphasis on coding style, modular and generic design. Studying VHDL language, with an emphasis on coding style, modular and generic design.

Project’s Goals (cont.) Studying and implementing topics in image processing, especially algorithms that can be implemented in real time video systems. Studying and implementing topics in image processing, especially algorithms that can be implemented in real time video systems.

Development Stages 1. Getting acquaintance with the environment of the system and understanding its designing tools. 2. Studying VHDL as mentioned before. 3. Gradually assembling the system:  System with no processing: receiving information from external source, sampling it and sending it out to be displayed on a digital monitor.

Development Stages (cont.)

 System with basic processing: Designing and implementing a component that converts between color spaces (RGB2YUV and YUV2RGB). Designing and implementing a component that converts between color spaces (RGB2YUV and YUV2RGB). Integrating this component to the system. Integrating this component to the system.

Development Stages (cont.) Basic Processing Unit Basic Processing Unit

Development Stages (cont.)  System using external memory for more complex processing, and memory management: Defining and designing an interface to the external memory, working as a frame buffer. Defining and designing an interface to the external memory, working as a frame buffer. Constructing memory management mechanism, implementing a frame buffer. Constructing memory management mechanism, implementing a frame buffer. Defining and implementing a display control unit. Defining and implementing a display control unit.

Processing Unit Processing Unit External Memory (fifo) External Memory (fifo) Memory Controller Memory Controller Display Controller Display Controller Video sync in Video sync out Video in Video out

Development Stages (cont.)  System with an advanced processing block (optional): Designing a scaling unit, or an adaptive filter unit, to be implemented on the design (the unit will be chosen depending on the project’s pace, and the preference of the project’s participants). Designing a scaling unit, or an adaptive filter unit, to be implemented on the design (the unit will be chosen depending on the project’s pace, and the preference of the project’s participants).

Advanced Processing Unit Advanced Processing Unit External Memory (fifo) External Memory (fifo) Memory Controller Memory Controller Display Controller Display Controller Video sync in Video sync out Video in Video out

Time Schedule Stage 1 of the development Stage 2 of the development Stage 3 of the development Semester A Semester B Writingsummeryreport

Time Schedule Semester A : Semester A : Stages 1,2 of the development stages. Starting stage 3 : designing the simple system (with no processing), and afterward the system with basic processing component. Semester B : Semester B : the rest of stage 3 :integrating an external memory and management it. advanced real time video processing.

Time Schedule in weeks till the midterm report: week 1: comprehending and defining the project goals. Week 2:studing the complex system and the design tools available. first encounter of the system. Preparing and available. first encounter of the system. Preparing and presenting the characterization report. presenting the characterization report. Week 3:preparing a detailed blocks diagram of the system Week 4:defining and characterizing the abstract generic block. Week 5:defining the memory and the display controllers interfaces.

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