Design of Networks with Limited Gate Fan-in If a two-level network realization requires more more gate Inputs than allowed, factoring the logic expression to obtain a multi-level realization is necessary. Example: Realize f(a,b,c,d) = S m(0,3,4,5,8,910,14,15) using three-input NOR gates. Soln.: -must use three-input NOR gates so factor expression for f’ and complement

Design of Networks with Limited Gate Fan-in When designing multiple-output networks with more than two levels, it is usually best to minimize each function separately. -- resulting two-level expressions are factored to increase number of levels -- factoring should be done in a way that introduces common terms. Example: Realize the given functions using only two-input NAND gates and inverters. Soln.: -functions to be realized and k-maps are shown

Design of Networks with Limited Gate Fan-in Example(cont’d): Realize the given functions using only two-input NAND gates and inverters. Soln.(cont’d): If we minimize each function separately the result is Factoring to reduce no. of gate inputs (while increasing no. of levels) Expression has common term -- preferred - common terms are underlined in the above expressions -the remaining 3-input gate in the f3 expression for can be eliminated using

Design of Networks with Limited Gate Fan-in Example(cont’d): Realize the given functions using only two-input NAND gates and inverters. Soln.(cont’d): Realization converted to NAND form Realization