1. Copyright © 2004 by Miguel A. Marin1 COMBINATIONAL CIRCUIT SYNTHESIS CLASSIC TWO-LEVEL CIRCUIT SYNTHESIS MULTILEVEL-CIRCUIT SYNTHESIS FACTORIZATION DECOMPOSITION CIRCUIT SYNTHESIS USING BUILDING BLOCKS SHARING BUILDING BLOCKS AMONG OUTPUT FUNCTIONS MULTIPLEXERS DECODERS LOOK-UP-TABLE LOGIC BLOCKS GENERAL SYNTHESIS METHOD

2. Copyright © 2004 by Miguel A. Marin2 CLASSIC TWO-LEVEL CIRCUIT SYNTHESIS PROCEDURE: THE WORD DESCRIPTION OF DESIRED BEHAVIOR IS GIVEN. THIS BEHAVIOR IS CONVERTED INTO SWITCHING (BOOLEAN) FUNTIONS WHICH LOGICLY RELATE INPUTS TO OUTPUTS. THESE FUNCTIONS ARE MINIMIZED TO OBTAIN A TWO-LEVEL CIRCUIT REALIZATION, USING STANDARD GATES FROM A COMPLETE SET, I.E. EITHER {AND,OR,NOT}, {NAND} OR {NOR} SETS.

3. Copyright © 2004 by Miguel A. Marin3 CLASSIC TWO-LEVEL CIRCUIT SYNTHESIS EXAMPLE: DESIGN A FULL-ADDER CIRCUIT. A full-adder is a device that adds in binary, three inputs, A, B, C in, and produces, two outputs: the sum, S, of the three inputs and the carry out, C out. C out = 1, when at least two inputs equal to 1. The output functions are: S = A  B  C in, C out = A B + A C in + B C in + A B C in Minimizing these functions, using k-maps or any other method,we obtain S = A  B  C in, C out = A B + A C in + B C in Using {AND,OR,NOT} gates, the minimal two level circuits are shown on next slide.

4. Copyright © 2004 by Miguel A. Marin4 CLASSIC TWO-LEVEL CIRCUIT SYNTHESIS EXAMPLE: DESIGN A FULL-ADDER CIRCUIT. (Continues)

5. Copyright © 2004 by Miguel A. Marin5 CLASSIC TWO-LEVEL CIRCUIT SYNTHESIS EXAMPLE: DESIGN A FULL-ADDER CIRCUIT. (Continues) Using {NAND} complete set, we obtain the circuit Remark: A two-level AND-OR circuit is transformed into a two- level NAND-NAND circuit by replacing AND, OR gates with NAND’s

6. Copyright © 2004 by Miguel A. Marin6 MULTILEVEL-CIRCUIT SYNTHESIS FACTORIZATION By finding common factors in the terms of the sum-of-products expression, it is possible to use gates with less fan-in. However, the resulting circuit has more propagation delay than the two- level-logic equivalent. For example: Consider the SUM function. If only two-input gates are available, then SUM = A  B  C in = (A !B + !A B) !C in + (!A !B + A B) C in = (A  B)  C in which produces the circuit

7. Copyright © 2004 by Miguel A. Marin7 MULTILEVEL-CIRCUIT SYNTHESIS FACTORIZATION (continues) Another example: The parity check circuit of 4 variables F(A,B,C,D) = A  B  C  D The Shannon Expansion with respect to A, B gives F = [C  D] !A !B + [C  D] !A B + [C  D] A !B + + [C  D] A B = (A  B)  (C  D) which produces a circuit that uses only two-input EX-OR gates.

8. Copyright © 2004 by Miguel A. Marin8 MULTILEVEL-CIRCUIT SYNTHESIS DECOMPOSITION IS A TECHNIQUE USED TO EXPRESS A GIVEN FUNCTION F IN TERMS OF ANOTHER FUNCTION G, WHICH COULD BE CONVENIENT, TO PRODUCE F. EXAMPLE: CONSIDER THE FUNCTION C OUT = A B + A C IN + B C IN CAN C OUT BE EXPRESSED AS A FUNCTION OF G = A  B ? TO ANSWER THIS QUESTION WE USE THE BRIDGING METHOD WHICH CONSISTS OF FINDING FUNCTIONS P AND R SUCH THAT C OUT = A B + A C IN + B C IN = P (A  B) + R

9. Copyright © 2004 by Miguel A. Marin9 MULTILEVEL-CIRCUIT SYNTHESIS DECOMPOSITION (THE BRIDGING METHOD) (Continues) C OUT = A B + A C IN + B C IN = P (A  B) + R WE CONSTRUCT K-MAPS FOR EACH ONE OF THE FUNCTIONS AND DETERMINE THE UNKOWN ENTRIES OF P AND R SUCH THAT THE EQUALITY FOR EACH ENTRY HOLDS C OUT P = C IN (A  B) R = A B ONE OF THE MANY EXISTING SOLUTIONS IS C OUT = C IN (A  B) + AB

10. Copyright © 2004 by Miguel A. Marin10 CIRCUIT SYNTHESIS USING BUILDING BLOCKS SHARING BUILDING BLOCKS AMONG OUTPUT FUNCTIONS ECONOMY OF CIRCUIT COMPONENTS (BUILDING BLOCKS) CAN BE ACHIEVED WHEN SHARING OF ONE OR MORE BUILDING BLOCKS IS POSSIBLE AMONG OUTPUT FUNCTIONS EXAMPLE: CONSIDER THE FULL-ADDER CIRCUIT. THE SUM FUNCTION USES TWO 2-INPUT EX-OR GATES. CAN THE C OUT FUNCTION SHARE ONE OF THEM, SAY Z = A  B? THE PROBLEM IS TO EXPRESS C OUT AS A FUNCTION OF Z

11. Copyright © 2004 by Miguel A. Marin11 CIRCUIT SYNTHESIS USING BUILDING BLOCKS SHARING BUILDING BLOCKS AMONG OUTPUTFUNCTIONS (Continues) The canonical sum-of-products expression of C out is C OUT = A B C IN + A B !C IN + A !B C IN + !A B C IN [1] The Shannon expansion of C OUT with respect to A,B is C OUT =[R 0 ] !A!B +[R 1 ] !AB+[R 2 ] A!B +[R 3 ] AB [2] FOR Z = A  B TO EXIST IN [2], R 1 MUST BE IDENTICAL TO R 2 AND TO C IN FOR [1] TO BE IDENTICAL TO [2], WE MUST HAVE R 3 = 1 AND R 0 =0 THE SOLUTION IS C OUT = C IN Z + A B OR C OUT = C IN (A  B) + A B

12. Copyright © 2004 by Miguel A. Marin12 CIRCUIT SYNTHESIS USING BUILDING BLOCKS DESIGNING WITH MULTIPLEXERS An m x 1 multiplexer, or m x 1 MUX, is a circuit with m = 2 n input lines, called data lines, one output line and n select input lines. Each combination of the select lines connects one and only one input data line to the output. The Shannon expansion is used to synthesize with multiplexers inputs select lines Enable signal used to activate, ENB = 1, or desactivate, ENB = 0, the circuit. output

13. Copyright © 2004 by Miguel A. Marin13 CIRCUIT SYNTHESIS USING BUILDING BLOCKS DESIGNING WITH MULTIPLEXERS (Continues) EXAMPLE: DESIGN A FULL ADDER WITH TWO 4 X 1 MUX’s The Shannon expansion of SUM and C out with respect to A,B are: SUM = [C in ] !A !B + [!C in ]!A B + [!C in ] A !B + [C in ]A B C out = [0] !A !B + [C in ]!A B + [C in ] A !B + [1] A B The resulting circuit is

14. Copyright © 2004 by Miguel A. Marin14 CIRCUIT SYNTHESIS USING BUILDING BLOCKS DESIGNING WITH MULTIPLEXERS (Continues) ANOTHER EXAMPLE: DESIGN A FULL ADDER WITH 2 X 1 MUX’s The resulting circuit is

15. Copyright © 2004 by Miguel A. Marin15 CIRCUIT SYNTHESIS USING BUILDING BLOCKS DESIGNING WITH MULTIPLEXERS (Continues) ANOTHER EXAMPLE: DESIGN A FULL ADDER WITH TWO 2 X 1 MUX’s AND ADDITIONAL GATES AT THE DATA LINES. THE SHANNON EXPANSION WITH RESPECT TO C IN GIVES SUM = [!A!B + A B] C IN + [A!B + !AB] !C IN = [A  B] C IN + [A  B] !C IN C OUT = [A + B] C IN + [AB] !C IN THE CORRESPONDING CIRCUIT IS

16. Copyright © 2004 by Miguel A. Marin16 CIRCUIT SYNTHESIS USING BUILDING BLOCKS DECODERS A DECODER IS A CIRCUIT WITH N INPUTS AND 2 N OUPTUTS. FOR EACH COMBINATION OF THE INPUTS, ONE AND ONLY ONE OUTPUTS IS ACTIVE. THE DEVICE CAN BE THOUGHT OF GENERATION ALL THE MINTEMS OF A BOOLEAN FUNCTION OF N VARIABLES. FOR N=3 IT IS REPRESENTED AS FOLLOWS 1-OUT-OF-8 DECODER 0123456701234567 ENB S1S1 S2S2 S3S3

17. Copyright © 2004 by Miguel A. Marin17 CIRCUIT SYNTHESIS USING BUILDING BLOCKS DECODERS (CONTINUES) EXAMPLE: DESIGN A FULL ADDER USING A 1-OUT-OT-8 DECODER. SUM =  m(1,2,4,7) Cout =  m(3,5,6,7) The circuit is

18. Copyright © 2004 by Miguel A. Marin18 CIRCUIT SYNTHESIS USING BUILDING BLOCKS LOOK-UP-TABLE LOGIC BLOCKS A LOOK-UP-TABLE CIRCUIT, OR LUT, IS A MULTIPLEXER WITH ONE STORAGE CELL AT EACH INPUT DATA LINE. THESE STORAGE CELL ARE USED TO IMPLEMENT SMALL LOGIC FUNTIONS. EACH CELL HOLDS EITHER A 0 OR A 1. THE SIZE OF A LUT IS DEFINED BY THE NUMBER OF INPUTS, WHICH ARE THE SELECT LINES OF THE MULTIPLEXER. EXAMPLE: A 3-LUT BUILT WITH AN 8 x 1 MUX THE CONTENTS OF THE STORAGE CELLS ARE WRITTEN INSIDE THE RETANGLE. THIS CONTENTS IS THE TRUTH TABLE OF THE FUNCTION TO BE PRODUCED BY THE 3-LUT. 8 storage cells

19. Copyright © 2004 by Miguel A. Marin19 CIRCUIT SYNTHESIS USING BUILDING BLOCKS LOOK-UP-TABLE LOGIC BLOCKS (continues) ANY 4-VARIABLE FUNCTION CAN BE PRODUCED WITH AT MOST THREE 3-LUTS. EXAMPLE: Produce the function F = !BC+!AB!C+B!CD+A!B!D The Shannon expansion with respect to A gives F = !A R !A + A R A = !A(!BC + B!C) + A(!BC+ B!CD + !B!D) NOTICE THAT F = !A R !A + A R A is of the form F = !a b + a c and should be produced by the output LUT. THE RESULTING CIRCUIT IS

20. Copyright © 2004 by Miguel A. Marin20 CIRCUIT SYNTHESIS USING BUILDING BLOCKS LOOK-UP-TABLE LOGIC BLOCKS (example continues) EXAMPLE: Produce the function F = !BC+!AB!C+B!CD+A!B!D The Shannon expansion with respect to B gives F = !B R !B + B R B = !B(C + A!D) + B(!A!C+ !CD) NOTICE THAT !R !B = R B AND, THEREFORE, ONLY TWO 3-LUTS ARE NEEDED. THE RESULTING CIRCUIT IS REMARK: AT THE PRESENT TIME, WE DO NOT KNOW ‘A PRIORI’ WHICH EXPANSION VARIABLE WILL PRODUCE THE MOST ECONOMICAL CIRCUIT. TRIAL AND ERROR METHOD IS THE BEST WE CAN DO.

21. Copyright © 2004 by Miguel A. Marin21 CIRCUIT SYNTHESIS USING BUILDING BLOCKS GENERAL SYNTHESIS METHOD GIVEN A BUILDING BLOCK G(x,y,…,z), IMPLEMENT F(A,B,…,T,R) USING ONLY BLOCKS G.

22. Copyright © 2004 by Miguel A. Marin22 CIRCUIT SYNTHESIS USING BUILDING BLOCKS GENERAL SYNTHESIS METHOD (CONTINUES) IF F IS NOT ANY OF THE INPUT VARIABLES A,B,C,…,T,R, THEIR COMPLEMENTS OR CONSTANT 0 OR CONSTANT 1, THEN THE OUTPUT F MUST COME FROM THE OUTPUT OF A BUILDING BLOCK G. SOLVING F = G FOR X, Y,…,Z AS FUNCTIONS OF A,B,C,…T,R WILL DETERMINE THE INPUTS TO THE OUTPUT BLOCK. THE METHOD IS ITERATED UNTIL THE INPUT VARIABLES, THEIR COMPLEMENTS OR CONSTANTS 0, 1 ARE FOUND. THIS METHOD IS INTENDED TO BE COMPUTERIZED AND USED AS PART OF A CAD SYSTEM