1 COMP541 Sequencing and Control Montek Singh Mar 29, 2007
2Topics Starting on Chapter 8 Control unit Multiplier as example Multiplier as example Today: hardwired control Next time: microprogrammed control
3 Control Units Two types Programmable Programmable Non-programmable (what you are implementing) Non-programmable (what you are implementing) Look at non-programmable first A multiplier A multiplier
4 Algorithmic State Machines Like a flowchart to express hardware algorithms ASM describes sequence of events and timing relationships Can then turn automatically into circuit
5 Components (3 of them) State box specifies a state And what register ops and/or outputs happen when in this state And what register ops and/or outputs happen when in this state
6 Decision Box Based on a single variable Paths for 0 and 1
7 Conditional Output Register operation is executed if box is reached after decision
8Example Somewhat like start of CPU
9 ASM Block Another example Machine idle until START Then A set to 0 Decision based on Q 0
10 Timing is Normal States change at clock (this is posedge clocked)
11 Example: Binary Multiplier Two versions Hardwired control Hardwired control Microprogrammed Microprogrammed Multiplies two unsigned binary numbers
12 Multiplication Algorithm Either select multiplicand or zero Shift left one each time Sum all to get product Result size 2n
13 Hardware-Friendly Variation Partial product Right shift Only n bit adder instead of 2n Each step either add/shift or just shift
14Datapath Counter size – ceiling of log n Holds multiplier as well as shifted result. How?
15More Counter preset to n- 1. Counts down. Signals when it hits zero.
16 ASM Chart Look at it in parts
17Idle Wait until G asserted Then clear C and A, and set P to n-1 Then multiplication begins
18Multiplication Test Q 0 If 1, add B If 1, add B Recall that MUL1 done all at same time What happens to C? What happens to C? Test counter zero To IDLE
19 Hardwired Control Two aspects to control 1. Control of the microoperations Generating signals, such as those for the ALU operations, register numbers, etc. Generating signals, such as those for the ALU operations, register numbers, etc. 2. Sequencing What happens next? What happens next? The order of any microoperations The order of any microoperations Like states of our locks Like states of our locks
20 Create Control Sig from ASM Can look at it one set at a time
21 Register A All microops on Reg A Last column is combinational expression that controls microop Signal name is just assigned by designer
22 Register B LOADB is not listed on ASM chart It’s an external signal that commands reg to load
23 Flip-Flop C
24 Register Q Similar External load External load Shift same as for Reg A Shift same as for Reg A
25 Counter P Both of counter’s Ops happen with others, so no new signals
26Sequencing Now can look purely at sequencing Only decisions affecting next state are left Q 0 did not affect state Q 0 did not affect state
27 Have State Diagram This should look familiar Similar to state diagram, such as used in your locks We’ll look at manual design briefly, then Verilog
28 What We Need to Do Have decided how to generate control signals Have separated control of timing Now: implement in logic
29 Sequence Register and Decoder Make register with enough bits to represent states Add decoder to generate signal for each state For our example (3 states) need 2-bit register 2-bit register 2-to-4 decoder (only need 3 lines of it) 2-to-4 decoder (only need 3 lines of it)
30 State Table Let’s recall how this works by stepping through
31 Generate Signals Using Tables
32Circuit
33 One-Hot Encoding (review) One Flip-Flop per state Only one of the FFs has value 1 Only one of the FFs has value 1 The single 1 propagates, controlled by combinational logic The single 1 propagates, controlled by combinational logic Seems wasteful at first glance Need n FFs instead of log n Need n FFs instead of log n However, it’s easy to design
34 Design from ASM Just use transformation rules to convert ASM to logic Here’s state box
35 Decision Box Represents both possibilities
36Junction Junction just an OR gate
37 Conditional Output The action is triggered by the generated control line
38 Circuit from Chart FFs labeled 1, decisions 2, junctions 3, control 4
39 Verilog Version Similar to the digital lock Case statement for sequence of states Transition to next state if criteria are true Transition to next state if criteria are true
40 Verilog (1) module binary_multiplier_v (CLK, RESET, G, LOADB, LOADQ, MULT_IN, MULT_OUT); input CLK, RESET, G, LOADB, LOADQ; input [3:0] MULT_IN; output [7:0] MULT_OUT; reg [1:0] state, next_state, P; parameter IDLE = 2'b00, MUL0 = 2'b01, MUL1 = 2'b10; reg [3:0] A, B, Q; reg C; wire Z; assign Z = ~| P; assign MULT_OUT = {A,Q};
41 Verilog (2) Reset or go to next state //state register CLK or posedge RESET) begin if (RESET == 1) state <= IDLE; else state <= next_state; end
42 Verilog (3) – Next State //next state function or Z or state) begin case (state) IDLE: if (G == 1) next_state <= MUL0; else next_state <= IDLE; MUL0: next_state <= MUL1; MUL1: if (Z == 1) next_state <= IDLE; else next_state <= MUL0; endcaseend
43 Verilog (4) – Datapath CLK) begin if (LOADB == 1) B <= MULT_IN; if (LOADQ == 1) Q <= MULT_IN; case (state) IDLE: if (G == 1) begin C <= 0; A <= 4'b0000; P <= 2'b11; endMUL0: if (Q[0] == 1) {C, A} <= A + B; MUL1:begin C <= 1'b0; A <= {C, A[3:1]}; Q <= {A[0], Q[3:1]}; P <= P - 2'b01; endendcaseend
44Simulation Multiply 1011 by 0110
45 My version has no next_state //state register CLK or posedge RESET) begin if (RESET == 1) state <= IDLE; else case (state) IDLE: if (G == 1) state <= MUL0; else state <= IDLE; MUL0: state <= MUL1; MUL1: if (Z == 1) state <= IDLE; else state <= MUL0; endcaseend
46Today We’ve taken example Created ASM Divided into control and sequencing Looked at two ways to implement using logic Looked at two ways to implement using logic Looked at Verilog example Looked at Verilog example Next time Look at microprogrammed control of multiplier Look at microprogrammed control of multiplier