Yefu Wang and Kai Ma

Project Goals and Assumptions Control power consumption of multi-core CPU by CPU frequency scaling Assumptions: Each core can be scaled individually Each core has a different frequency-power curve

Progresses System design Initial results on modeling Experimental setup Real system experiment Simulation Initial experimental results CPU Power sensor Temperature sensors Controller Power set point Frequency modulator Per-core frequency level CPU Power Per-core Temperature

System Design: Over Heating Protection Basic idea: using temperature as a constraint. In each control period, the control signal (frequency of each core) should not exceed its safe region. Method: model based prediction.

Initial Results on Modeling Power model Use the same model as a recent paper Temperature model Use similar model described in a previous paper Future work: derive such an linear constraint from a temperature model: We may change these soon Xiaorui Wang, and Ming Chen, "Cluster-level Feedback Power Control for Performance Optimization", the 14th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2008) Kevin Skadron, Tarek F. Abdelzaher, Mircea R. Stan: Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management. HPCA 2002 tp: Total power of all cores d: Frequency change M, C: Constant

Optimization Problem Physical frequency Core grouping Power budget Overheating protection Control AccuracyPerformance optimization s.t. Minimize:

Experimental Setup (1) CPU Intel Xeon 5365 Per-core frequency scaling support? Core 0Core 1 Core 2Core 3Power 3G 215.9W 2G3G 215.9W 2G3G 208.5W 2G 3G208.2W 2G 184.0W

Experimental Setup (2) Power monitor: big picture Wu, W., etc A systematic method for functional unit power estimation in microprocessors. In Proceedings of the 43rd Annual Conference on Design Automation Canturk Isci, Margaret Martonosi, Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture

Experimental Setup (3) Power monitor CPU power supply Current clamp (clamp on meter) Digital multi-meter USBTMC device driver (USB Test & Measurement Class ) Temperature monitor lm-sensors interface Core-temp device driver

Simulation Setup (1) Simulation methodology: SESC+Wattch+CACTI+Orion+HotSpot SESC SESC is a cycle accurate architectural simulator. It models a very wide set of architectures: single processors, CMPs, PIMs, and thread level speculation. To get CPU working status, like how instructions are decoded by instruction decoder, and the working status of branch prediction unit, pipeline, stage, memory access record.

Simulation Setup (2) Watth “WATTCH” is an architectural simulator that estimates CPU power consumption. CACTI CACTI is an integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. Most useful paper is the official technical report released by HPL Orion The most useful paper: Orion A Power-Performance Simulator for Interconnection Networks

Simulation Setup (3) HotSpot HotSpot is an accurate and fast thermal model suitable for use in architectural studies. The most useful papers: 1 A static power model for architects 2 Wattch: A framework for architectural-level power analysis and optimizations

How They Work Together Our approach: use SESC as framework Specifically, wrap Wattch,CACTI, Orion, HotSpot, each one into one function separately,and call these functions in one callback function in SESC thermal class.

How to Scale Processor Base on GaThermAMD and Alpha Floor plan

Initial Experimental Results Ad-hoc controller Keeping CPU frequencies of all cores to be the same If Power > set point frequency-=step; Else frequency+=step; Force_CPU_frequency (frequency);

Who Is Doing What Yefu WangKai Ma Real system set upSimulation set up System design Real system experimentsSimulation experiments Next Step: Theoretical Controller