1. 1 Overview 1.Motivation (Kevin) 1.5 hrs 2.Thermal issues (Kevin) 3.Power modeling (David) 1.5 4.Thermal management (David) hrs 5.Optimal DTM (Lev).5 hrs 6.Clustering (Antonio) 1 hr 7.Power distribution (David) 15 min 8.What current chips do (Lev) 45 min 9.HotSpot and sensors (Kevin) 1 hr

2. 2 What current chips do Power and thermal management

3. 3 Controllers Inputs (power, temperature, etc.) Response time Tuning Simplicity of implementation Performance, reliability Power management / thermal management

4. 4 Controllers (cont’d) A non-trivial tradeoff PerformanceReliability Cost

5. 5 Real processors: IBM* PowerPC* G3/G4 Cache throttling IBM Power5 two-step response –Mild response, then aggressive response –Details unknown [ISSCC’04], but one may be fetch gating –Target temp. appears to be 85° AMD* PowerNow!* Technology Transmeta* Longrun* technology Intel® SpeedStep® technology Enhanced Intel® SpeedStep technology * Other names and brands may be claimed as the property of others

6. 6 PowerPC G3 Microprocessor On-chip temperature sensor (junction temperature) –Based on differential voltage change across 2 diodes of different sizes –Implemented in PowerPC G3/G4 processors OS required for control Instruction Cache Throttling used to dynamically lower junction temperature

7. 7 Transmeta LongRun ** LongRun power management –Code Morphing* software (processor- internal) –Performance demands are determined by sampling the idle time Crusoe * processor *** –Voltage changes in steps of 25 mV –Frequency changes in steps of 33 MHz *Other names and brands may be claimed as the property of others ** Source: http://www.transmeta.comhttp://www.transmeta.com *** Data dated 2001

8. 8 Transmeta LongRun (cont’d) Idle time  decrement V&f Activity  increment V&f (if possible) Performance mode  V&f adjustment Source: http://www.transmeta.com/crusoe/longrun.html

9. 9 Previous Intel microprocessors 1 Thermal monitor mechanism A two-point mechanism using voltage scaling (for battery life) 1 Information on Intel microprocessors is based on Efraim Rotem’s presentation in the TACS workshop 06/2004

10. 10 Thermal monitor Based on clock throttling Full operational mode: maximal frequency Minimal operation mode: clocks are stalled for a part of the duty cycle Activation options: –By OS (e.g., ACPI) –By a special hardware

11. 11 Thermal Monitor (cont.) Trip Point is calibrated at manufacturing time Simple response (example) –Turn processor clocks on/off at OS or hardware selected duty cycle, eg 50% –eg, 2  s on + 2  s off?

12. 12 Static voltage scaling (for battery life) Performance mode –Maximal frequency & Vcc –AC outlet or set by user Power saving mode –Low frequency & Vcc –Upon request or while the user changed the usage mode

13. 13 The Intel Pentium® M Processor Targets the mobile market Improved power efficiency Advanced ACPI interface Enhanced SpeedStep architecture

14. 14 DVS in the Pentium M Processor Changes both voltage and frequency at the runtime Efficiently switches between different DVS control points

15. 15 Thermal sensors Two thermal sensors Maximal temperature reached  throttling Critical shutdown point reached  shutdown

16. 16 Operation modes Software control mechanism (e.g., ACPI) –Track the junction temperature –Initiate the appropriate policy Self throttle –Digital temperature detector initiates one of the power control cycles –Used as a fail-safe mechanism since it is much faster than the software

17. 17 Enhanced Intel SpeedStep technology Implements DVS Upon a thermal trigger or SW request, CPU halts execution and locks PLL at a new frequency (a few  sec) Once finished, the Vcc starts changing to the new value (order of 1mV/  sec) Transition up is done in the reverse order

18. 18 DVS cycle

19. 19 DVS transitions Frequency transition is fast enough to allow non-interrupted application execution DVS transitions can be utilized for energy and thermal control during the normal operation flow The target frequency and voltage are programmable by BIOS or OS Support for multiple voltage/ frequency points

20. 20 Adaptive policy (for battery life) Uninterrupted power state transition User selectable policy Increases frequency on demand, and decreases power and frequency while idle for a long time

21. 21 Info More specific information on Pentium M will be available at Efraim Rotem’s presentation in the TACS workshop 06/2004 (tomorrow)

22. 22 ACPI and OSPM 1 ACPI = Advanced Configuration and Power Interface (an open industry specification) OSPM = Operating System-directed configuration and Power Management Cooling decisions are based on the application load and the thermal heuristics of the system 1 Source: The ACPI specification 2.0, see http://www.acpi.info/

23. 23 Cooling policies Active cooling – a direct action by OSPM (e.g., turning on a fan) Passive cooling – reducing the power consumption (e.g., throttling) Critical trip points – shutdown

24. 24 Example of SW-based clock throttling  P[%] = _TC1 * (T n – T n-1 ) + _TC2 * (T n –T t ) T n – current temperature T t – target temperature P n = P n-1 + HW[-  P] Pn is in % The coefficients are set by the OEM