CS61C L26 Single Cycle CPU Datapath II (1) Garcia © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 26 – Single Cycle CPU Datapath II 98,389 UC Identity thefts?!  newscenter.berkeley.edu/security/grad/ A laptop was stolen from Grad division with names, SS #, birth dates of almost 10 6 former grad students at UC Berkeley. The thief may not know what they have! Sensitive data allowed on portables? Good idea…NOT!

CS61C L26 Single Cycle CPU Datapath II (2) Garcia © UCB How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic (hard part!)

CS61C L26 Single Cycle CPU Datapath II (3) Garcia © UCB Step 3: Assemble DataPath meeting requirements Register Transfer Requirements  Datapath Assembly Instruction Fetch Read Operands and Execute Operation

CS61C L26 Single Cycle CPU Datapath II (4) Garcia © UCB 3a: Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: -Sequential Code: PC = PC + 4 -Branch and Jump: PC = “something else” 32 Instruction Word Address Instruction Memory PCClk Next Address Logic

CS61C L26 Single Cycle CPU Datapath II (5) Garcia © UCB 3b: Add & Subtract R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers RsRtRd ALU oprsrtrdshamtfunct bits 5 bits We’ve already defined register file, ALU

CS61C L26 Single Cycle CPU Datapath II (6) Garcia © UCB Clocking Methodology Storage elements clocked by same edge Being physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF, and we have the usual clock-to-Q delay “Critical path” (longest path through logic) determines length of clock period Clk

CS61C L26 Single Cycle CPU Datapath II (7) Garcia © UCB Register-Register Timing: One complete cycle 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

CS61C L26 Single Cycle CPU Datapath II (8) Garcia © UCB 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] 32 Result ALUct r Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs ZeroExt Mux RtRd RegDst Mux imm16 ALUSrc ALU 11 oprsrtimmediate bits16 bits5 bits rd? immediate bits Rt? Already defined 32-bit MUX; Zero Ext? What about Rt register read??

CS61C L26 Single Cycle CPU Datapath II (9) Garcia © UCB 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs RtRd RegDst Extender Mux imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mu x W_Src ?? Rt

CS61C L26 Single Cycle CPU Datapath II (10) Garcia © UCB 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU 32 Mux W_Src

CS61C L26 Single Cycle CPU Datapath II (11) Garcia © UCB 3f: The Branch Instruction beq rs, rt, imm16 mem[PC] Fetch the instruction from memory Equal = R[rs] == R[rt] Calculate branch condition if (Equal) Calculate the next instruction’s address -PC = PC ( SignExt(imm16) x 4 ) else -PC = PC + 4 oprsrtimmediate bits16 bits5 bits

CS61C L26 Single Cycle CPU Datapath II (12) Garcia © UCB Datapath for Branch Operations beq rs, rt, imm16 Datapath generates condition (equal) oprsrtimmediate bits16 bits5 bits 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Equal? Cond PC Ext Inst Address Already MUX, adder, sign extend, zero

CS61C L26 Single Cycle CPU Datapath II (13) Garcia © UCB Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction Imm16RdRtRs = Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory

CS61C L26 Single Cycle CPU Datapath II (14) Garcia © UCB An Abstract View of the Implementation Data Out Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

CS61C L26 Single Cycle CPU Datapath II (15) Garcia © UCB Peer Instruction A. Our ALU is a synchronous device B. We could have used tri-state devices instead of a MUX to feed busW, the register write data line C. The ALU is inactive for memory reads or writes. ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

CS61C L26 Single Cycle CPU Datapath II (16) Garcia © UCB °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Control is the hard part °Next time! Summary: Single cycle datapath Control Datapath Memory Processor Input Output