May. 04, 2007General Oral Examination1 Gate-Level Test Generation Using Spectral Methods at Register-Transfer Level Committee Members: Prof. Victor P. Nelson Prof. Adit D. Singh Prof. Charles E. Stroud Nitin Yogi – PhD Thesis Proposal May 04, 2007, 3 p.m. Advisor: Prof. Vishwani D. Agrawal

May. 04, 2007General Oral Examination2 Outline 1. Introduction 2. Background 3. Spectral Register Transfer Level (RTL) test generation 4. RTL Design for Testability (DFT) 5. Results 6. Future Work 7. Conclusion

May. 04, 2007General Oral Examination3 1 - Introduction  Test generation challenges  Test generation methods  Problem definition

May. 04, 2007General Oral Examination4 1.1 – Test Generation Challenges  Two main challenges Reducing test generation complexity  Majority circuits sequential in nature  Rise in design complexity Good quality test vectors  High fault coverage  Low yield loss

May. 04, 2007General Oral Examination5 1.2 – Test Generation Methods  Scan-Based Test Generation  Sequential Test Generation  Register-Transfer Level (RTL) Test Generation  Pseudo Functional Test Generation

May. 04, 2007General Oral Examination – Scan-Based Test Generation Combinational Logic FF Circuit Inputs Circuit Outputs Scan Input Scan Output Scan chain FF Functional Scan Scan FF

May. 04, 2007General Oral Examination – Scan-Based Test Generation  Advantages: Reduced test generation complexity  Combinational test generation High fault coverage  Disadvantages: Area overhead (~ 5 – 10%) Timing overhead (~ 5 – 10%) Non-functional tests  Long test times  Issues from high test power Voltage droop Ground bounce Issues with at-speed scan tests  False and multi-cycle paths

May. 04, 2007General Oral Examination – Sequential Test Generation  Non-scan test generation  Advantages Functional vectors  Short test times  No test power issues Ability to generate at-speed tests  Disadvantages High test generation complexity

May. 04, 2007General Oral Examination – RTL Test Generation  Earlier Work [Jha et.al.,Hayes et. al.,Goloubeva et. al.]  Advantages: Low test generation complexity  Less amount of information to process Early detection of testability issues Synthesis independent  Disadvantages: Main issues  Closing gap between RTL and gate-level coverage  High engineering effort No established method

May. 04, 2007General Oral Examination – Pseudo Functional Test Generation  Weighted random vectors (Brglez et. al.) Test vectors generated with certain probabilities of being logic ‘0’ or ‘1’  PROPTEST (Guo et. al.) Property based test generation Probabilities, holding, perturbation  Spectral methods (Giani et. al., Khan et. al.) Test generation using spectral properties  Retrieve spectral properties  Generate new vectors with those properties

May. 04, 2007General Oral Examination – Problem Definition  Summary of goals Generate functional test vectors  Sequential test generation Low test generation complexity  RTL test generation Convenient test generation method  Spectral methods  Hence the problem is … To generate function vectors using sequential test generation by using spectral methods at RTL

May. 04, 2007General Oral Examination12 Outline 1. Introduction 2. Background 3. Spectral Register Transfer Level (RTL) test generation 4. RTL Design for Testability (DFT) 5. Results 6. Future Work 7. Conclusion

May. 04, 2007General Oral Examination13 2 – Background  Spectral analysis for test generation  Walsh functions and Hadamard matrix

May. 04, 2007General Oral Examination – Spectral Analysis for Test Generation  Spectral analysis: Interpret information in frequency domain  Test generation Good quality test vectors exhibit certain spectral characteristics Goals:  Determine relevant spectral characteristics  Generate vectors with those characteristics

May. 04, 2007General Oral Examination Walsh functions and Hadamard matrix w0w0 w1w1 w2w2 w3w3 w4w4 w5w5 w6w6 w7w7 Walsh functions (order 8) time H 8 = Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit-stream. Walsh functions form the rows of a Hadamard matrix. Example of Hadamard matrix of order 8 Move to next section

May. 04, 2007General Oral Examination16 Outline 1. Introduction 2. Background 3. Spectral Register Transfer Level (RTL) test generation 4. RTL Design for Testability (DFT) 5. Results 6. Future Work 7. Conclusion

May. 04, 2007General Oral Examination17 3 – Spectral RTL Test Generation  Spectral characterization  Spectral vector generation  Test set minimization

May. 04, 2007General Oral Examination – Spectral Characterization  Purpose – Determine relevant spectral characteristics  Premise – Vectors detecting RTL faults exhibit important spectral characteristics  Steps RTL fault modeling and test generation Spectral analysis

May. 04, 2007General Oral Examination – RTL Fault Modeling Combinational Logic FF Inputs Outputs RTL fault sites A circuit is an interconnect of several RTL modules.

May. 04, 2007General Oral Examination – Spectral Analysis 0 to -1 Bit-stream Vector 1 Vector 2. Input 1 Input 2. Bit-stream of Input 2

May. 04, 2007General Oral Examination – Spectral Analysis (cont.) Bit stream to analyze Correlating with Walsh functions by multiplying with Hadamard matrix. Essential component (others regarded noise) Hadamard Matrix H(3) Bit stream Spectral coeffs.

May. 04, 2007General Oral Examination22 Power Spectrum: “Ready” Signal Noise level (1/128) Examples of Essential components Examples of Noise components Normalized Power Spectral Coefficients PARWAN Processor Circuit

May. 04, 2007General Oral Examination23 Power Spectrum: A Random Signal Normalized Power Noise level (1/128) Spectral Coefficients

May. 04, 2007General Oral Examination – Spectral Vector Generation Perturbation Generation of new bit-stream by multiplying with Hadamard matrix Spectral components Essential component retained noise components randomly perturbed New bit stream Bits changed Sign function -1 to 0

May. 04, 2007General Oral Examination – Test Set Minimization  Fault simulation of new sequences Set of perturbation vector sequences {V 1, V 2,.., V M } are generated. Vector sequences are fault simulated and faults detected by each is obtained.  Minimization problem Find minimum set of vector sequences covering all the detected faults. Minimize Count{V 1, …,V M } to obtain compressed seq. {V 1,…,V C } Fault Coverage{V 1, …,V C } = Fault Coverage{V 1, …,V M } Compaction problem formulated as an Integer Linear Program (ILP) *. * P. Drineas and Y. Makris, “Independent Test Sequence Compaction through Integer Programming," Proc. ICCD’03, pp

May. 04, 2007General Oral Examination – ILP test minimization  Set of integer [0,1] variables { t j } – one for each vector sequence t j = 0: drop sequence ; t j = 1: select sequence  Set of constraints { c k } – one for each fault Example: for k th fault detected by vector sequences u, v and w c k : t u + t v + t w ≥ 1  Objective function Minimize ∑ t j ; j = 1 to N

May. 04, 2007General Oral Examination – Hybrid LP – ILP  Approximate solution to ILP (Relaxed LP, Rounding)*  Algorithm: 1. All variables redefined as real [0,1] real variables (LP model) 2. Loop : 1. Solve LP 2. Round variables to add constraints 1. Round to 0 if ( 0.0 < variables ≤ 0.1) 2. Round to 1 if ( 0.9 ≤ variables < 1.0) 3. Exit loop if no variables are rounded 3. Reconvert variables to [0,1] integers and solve ILP * Kantipudi, K.R.; Agrawal, V.D, “A Reduced Complexity Algorithm for Minimizing N-Detect Tests”, 20th International Conference on VLSI Design, 2007

May. 04, 2007General Oral Examination28 Outline 1. Introduction 2. Background 3. Spectral Register Transfer Level (RTL) test generation 4. RTL Design for Testability (DFT) 5. Results 6. Future Work 7. Conclusion

May. 04, 2007General Oral Examination29 4 – RTL Design for Testability  Goals of DFT: Improve fault coverage  XOR tree as DFT Low area overhead Low performance penalty Does not change state machine  Hard-to-detect RTL faults used for observation test points Hard-to-detect RTL faults To test output XOR tree

May. 04, 2007General Oral Examination30 Outline 1. Introduction 2. Background 3. Spectral Register Transfer Level (RTL) test generation 4. RTL Design for Testability (DFT) 5. Results 6. Future Work 7. Conclusion

May. 04, 2007General Oral Examination31 5 – Results  Experimental Circuits  Spectral RTL test generation Stuck-at faults Transition delay faults

May. 04, 2007General Oral Examination – Experimental Circuits  Experimental Circuits 4 ITC’99 high level RTL circuits 4 ISCAS’89 circuits. PARWAN processor*  Commercial sequential ATPG tool Mentor Graphics FlexTest for test generation and fault simulation.  Results obtained on Sun Ultra 5 machines with 256MB RAM. CircuitbenchmarkPIsPOsFFs b01 ITC ’ b09 ITC ’ b11 ITC ’ b14 ITC ’ s1488ISCAS’ s5378ISCAS’ s9234ISCAS’ s35932ISCAS’ PARWANprocessor * Z. Navabi, VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill, 1993.

May. 04, 2007General Oral Examination – ATPG for stuck-at faults

May. 04, 2007General Oral Examination34 PARWAN* Processor * Z. Navabi, VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill, 1993.

May. 04, 2007General Oral Examination35 Results – Test Generation Circuit name # gate- level faults RTL-ATPG spectral testsFlexTest Gate-level ATPGRandom inputs Cov. (%) No. of vectors CPU $ (secs) Cov. (%) No. of vectors CPU $ (secs) No. of vectors Cov (%) b09-A b09-D b11-A b11-D b s s s5378* s PARWAN * Reset input added. $ Sun Ultra 5, 256MB RAM

May. 04, 2007General Oral Examination36 Results – Test Generation and RTL DFT Circuit RTL Spectral ATPG Gate-level ATPG (FlexTest) Random vecs. Cov. (%) No. of vecs. CPU* (secs) Cov. (%) No. of vecs. CPU* (secs) Cov. (%) No. of vecs. Parwan 98.23% % %2814 Parwan (with DFT) 98.77% % %2948 *Sun Ultra 5, 256MB RAM

May. 04, 2007General Oral Examination – ATPG for transition faults

May. 04, 2007General Oral Examination38 Results – Test Generation ATPG used Version of PARWAN circuit CPU secs.* No. of vectors Stuck-at fault cov. (%) Transition fault cov. (%) RTL-spectral for transition faults Original DFT for t-f Gate-level FlexTest for transition faults Original DFT for t-f Random vectors Original DFT for s-a-f * Sun Ultra 5, 256MB RAM s-a-f: stuck-at faults t-f : transition faults

May. 04, 2007General Oral Examination39 Outline 1. Introduction 2. Background 3. Spectral Register Transfer Level (RTL) test generation 4. RTL Design for Testability (DFT) 5. Results 6. Future Work 7. Conclusion

May. 04, 2007General Oral Examination40 6 – Future Work  Fourier Analysis of Digital Waveforms  Spectral BIST

May. 04, 2007General Oral Examination – Fourier Analysis of Digital Waveforms  Fourier Transform – converts signals to frequency domain  Digital bit-streams can be perceived as sampled analog signals  Important properties (not exhibited by Walsh functions) Frequency decomposition using Fourier transform is invariant to phase or circular time-shift Multiplication = Convolution (frequency domain) (time domain)  Other advantages of Fourier Transform over Walsh Established methods for noise analysis Methods to find Power Spectral Density (PSD)

May. 04, 2007General Oral Examination42 Wrapper – Built-In Self Test  Built-In Self Test (BIST) Hardware inserted to:  Generate test vectors  Capture responses of CUT  Flag CUT good or bad Circuit Under Test (CUT) Test generator System Inputs System Outputs Response Analyzer CUT status

May. 04, 2007General Oral Examination43 Motivation for Spectral BIST  BIST Advantages:  No need of expensive Automatic Test Equipment (ATE)  Testing during operation and maintenance  Supports system level test  Supports at-speed testing  And many more … Disadvantages:  Low coverage test vectors  Area / timing overhead  Problem is… To design a test pattern generator with spectral information that generates high coverage test vectors

May. 04, 2007General Oral Examination44 Fourier Transform of Test Bit-Stream Prominent features

May. 04, 2007General Oral Examination – Spectral BIST Wrapper Circuit Under Test (CUT) Test generator System Inputs Response Analyzer CUT status Spectral Filter System Outputs Spectral Test Generator

May. 04, 2007General Oral Examination46 Digital Filter Design  If y : output of filter x : input of filter n : time period p : order of filter Infinite Impulse Response (IIR)  y(n) = f (y(n-1), ….. y(n-p), x(n), x(n-1), … x(n-p)) Finite Impulse Response (FIR)  y(n) = f (x(n), x(n-1), … x(n-p))  IIR would require more hardware than FIR

May. 04, 2007General Oral Examination47 Spectral Test Generator Test generator Spectral Filter Spectral Test Generator LFSR FIR filter

May. 04, 2007General Oral Examination48 FIR Filter Design FIR filter

May. 04, 2007General Oral Examination49 FIR filtering Random bit-stream Random bit-stream after filtering Filter

May. 04, 2007General Oral Examination50 How good is the filtered bit-stream ? Original test bit-streamRandom bit-stream after filtering

May. 04, 2007General Oral Examination51 Results - Comparison Test Set No. of vectors No. of faults detected Total no. of faults Test cov. (%) RTL vectors % Flextest vectors % Random vectors % Filtered vectors % s382 s526 Test Set No. of vectors No. of faults detected Total no. of faults Test cov. (%) RTL vectors % Flextest vectors % Random vectors % Filtered vectors %

May. 04, 2007General Oral Examination52 Results – Graphs

May. 04, 2007General Oral Examination53 Results – Graphs

May. 04, 2007General Oral Examination54 Conclusion  We have presented a new method for gate-level test generation using spectral methods at RTL  Proposed Spectral RTL ATPG technique applied to ITC’99 and ISCAS’89 benchmarks, and a processor circuit  In most cases, Spectral RTL ATPG gave similar or better test coverage in shorter CPU time as compared to commercial sequential ATPG tool FlexTest  Proposed RTL DFT technique enhanced fault coverages

May. 04, 2007General Oral Examination55 Conclusion – Future Work  Investigate Fourier analysis of digital bit- streams Compare Walsh and Fourier analysis Investigate their use for signature analysis  Research on spectral test generator for BIST Experiment with different designs of LFSR Efficient design of spectral filter

May. 04, 2007General Oral Examination56 Questions ? Thank You !