Arithmetic II CPSC 321 E. J. Kim

Today’s Menu Arithmetic-Logic Units Logic Design Revisited Faster Addition Multiplication (if time permits)

Goals We recall some basic logic gates Determine the truth tables for the Boolean functions We recall half-adders and full-adders Ripple-carry adders Discuss faster adders

Logic Gates AND gate OR gate NOT gate What are the truth tables?

Logic Gates NOR gate NAND gate XOR gate What are the truth tables?

Half Adder s c a b a b c s

Full Adder c in a b c out s Give a Boolean formula for s s=cin xor a xor b Give a Boolean formula for c out c out =ab+c in (a xor b) Design now a circuit using and, or, xor.

Full Adder c in a b c out s s=c in xor a xor b c out = ab+c in (a xor b)

Ripple Carry Adder

Critical Path c in a b c out s Suppose that each gate has a unit delay. What is the critical path (= path with the longest delay)?

Ripple Carry Adders Each gates causes a delay our example: 3 gates for carry generation book has example with 2 gates Carry might ripple through all n adders O(n) gates causing delay intolerable delay if n is large Carry lookahead adders

Faster Adders c in a b c out s c out =ab+c in (a xor b) =ab+ac in +bc in =ab+(a+b)c in = g + p c in Generate g = ab Propagate p = a+b Why are they called like that?

Fast Adders Iterate the idea, generate and propagate c i+1 = g i + p i c i = g i + p i (g i-1 + p i-1 c i-1 ) = g i + p i g i-1 + p i p i-1 c i-1 = g i + p i g i-1 + p i p i-1 g i-2 +…+ p i p i-1 …p 1 g 0 +p i p i-1 …p 1 p 0 c 0 Two level AND-OR circuit Carry is known early!

Carry Lookahead Adders Based on the previous identity Fast because critical path is shorter O(log n) gate delays [assuming 2-input gates]  More complex to implement  Design is less regular  Layout of one bit adder cells depend on i Compromise  couple blocks of carry lookahead adders

Building an ALU Addition Subtraction AND OR What is missing?

Need to support the set-on-less-than instruction (slt) remember: slt is an arithmetic instruction produces 1 if rs < rt and 0 otherwise use subtraction: (a-b) < 0 implies a < b Need to support test for equality (beq $t5, $t6, $t7) use subtraction: (a-b) = 0 implies a = b Tailoring the ALU to the MIPS

SLT Determine a<b Calculate b-a If MSB equals 1, then a<b 0, then a>=b Changes? Operation less than Output of subtraction Overflow

SLT 4 operations subtraction output available Connect MSB set output w/ LSB less

LSB indicates whether a<b 0 if false 1 if true

Test for equality Notice control lines: 000 = and 001 = or 010 = add 110 = subtract 111 = slt Note: zero is a 1 when the result is zero!

Summary We can build an ALU to support the MIPS instruction set key idea: use multiplexor to select the output we want we can efficiently perform subtraction using two’s complement we can replicate a 1-bit ALU to produce a 32-bit ALU Important points about hardware all of the gates are always working the speed of a gate is affected by the number of inputs to the gate the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) We focused on basic principles. We noted that clever changes to organization can improve performance (similar to using better algorithms in software) faster addition, next time: faster multiplication