MICE Tracker Readout Overview channel AFE II-t boards - 8 Visible Light Photon Counter (VLPC) cassettes - 4 cryostats

MICE Tracker Readout Overview - Final data destination: VME LVDS Serdes Buffer (VLSB) banks via Low Voltage Differential Signaling (LDVS) links. - KEK test beam data readout to VLSB banks: One trigger at a time. - VLSB firmware needs to be modified for MICE. (~600 muon triggers per 1 ms wide spill)

AFE-IIt Component Overview TriP-t (Trigger and Pipeline with time) –32 channel, fully custom, mixed signal ASIC –Receives amplified signals from VLPCs –Main functions Provide prompt discriminator bitmap to digital FPGA (DFPGA) Provide, on demand, analog charge and time information stored in pipeline from earlier event, to ADCs DFPGA AFPGA ADC TriP-t ¼ of AFE-IIt board Data from VLPCs

AFE-IIt Component Overview ADC –Dual channel, 10-bit, 20 Msamples/sec –Digitizes analog charge and time signals from TriP-t chips upon receipt of trigger –Sends digitized data to AFPGAs DFPGA AFPGA ADC TriP-t ¼ of AFE-IIt board

AFE-IIt Component Overview AFPGA (Analog FPGA) –Controls operation of ADCs and TriP-t chips –Will receive discriminator bitmap from DFPGA and send processed data to DFPGA Part of MICE firmware development Necessary for increased data throughput DFPGA AFPGA ADC TriP-t ¼ of AFE-IIt board

AFE-IIt Component Overview DFPGA AFPGA ADC TriP-t DFPGA (Digital FPGA) –Will send discriminator bitmap to AFPGA –After AFPGA processes data, DFPGA will Receive data from AFPGA Send data to VLSB banks along LVDS links Part of MICE firmware development Necessary for increased data throughput Data to VLSB ¼ of AFE-IIt board

AFE-IIt Firmware Modifications for MICE Increase data throughput to ~600 muons every 1 ms wide spill. –Modify AFPGA signals which control TriP-t chips and ADCs. Terry Hart’s talk –Send discriminator bitmap from DFPGAs to AFPGAs. Senerath Galagedera’s talk Redirect data to VLSB banks. Terry Hart’s talk