Aug 31, '02VDAT'02: Low-Power Design1 Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja, Rutgers.

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Presentation transcript:

Aug 31, '02VDAT'02: Low-Power Design1 Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja, Rutgers University Vishwani D. Agrawal, Agere Systems Michael L. Bushnell, Rutgers University Bangalore, August 31, 2002

Aug 31, '02VDAT'02: Low-Power Design2 Problem Statement Design a digital circuit for minimum transient energy consumption by eliminating hazards

Aug 31, '02VDAT'02: Low-Power Design3 Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition Ref: Agrawal, et al., Proc. VLSI Design’99

Aug 31, '02VDAT'02: Low-Power Design4 Given that events occur at the input of a gate (inertial delay = d ) at times t 1 <... < t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t d t n - t 1 + d t n - t 1 + d t 1 t 2 t 3 t n t n + d t 1 t 2 t 3 t n t n + d time time

Aug 31, '02VDAT'02: Low-Power Design5 Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

Aug 31, '02VDAT'02: Low-Power Design6 Linear Program (LP) Variables: gate and buffer delays Objective: minimize number of buffers Subject to: overall circuit delay Subject to: minimum transient condition for multi-input gates AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)

Aug 31, '02VDAT'02: Low-Power Design7 Limitations of This LP Constraints are written by path enumeration. Since number of paths in a circuit is exponential in circuit size, the formulation is infeasible for large circuits. Example: c880 has 6.96M constraints.

Aug 31, '02VDAT'02: Low-Power Design8 A New LP Model Introduce two new variables per gate output: t i Earliest time of signal transition at gate i. T i Latest time of signal transition at gate i. t 1, T 1 t n, T n t i, T i

Aug 31, '02VDAT'02: Low-Power Design9 New Linear Program Gate variables d 4..d 12 Buffer Variables d 15..d 29 Corresponding window variables t 4..t 29 and T 4..T 29.

Aug 31, '02VDAT'02: Low-Power Design10 Multiple-Input Gate Constraints For Gate 7: T 7 > T 5 + d 7 ; t 7 T 7 - t 7 ; T 7 > T 6 + d 7 ; t 7 < t 6 + d 7 ;

Aug 31, '02VDAT'02: Low-Power Design11 Single-Input Gate Constraints T 16 + d 19 = T 19 ; t 16 + d 19 = t 19 ; Buffer 19:

Aug 31, '02VDAT'02: Low-Power Design12 Overall Delay Constraints T 11 < maxdelay T 12 < maxdelay

Aug 31, '02VDAT'02: Low-Power Design13 Validation of the Model For Gate 6 (path-enumeration model): d 1 + d 3 – d 2 < d 6 d 2 – d 3 – d 1 < d 6

Aug 31, '02VDAT'02: Low-Power Design14 Validation of the Model For Gate 6 (new model): T 6 > T 2 + d 6 ; t 6 T 6 - t 6 ; T 6 > T 3 + d 6 ; t 6 < t 3 + d 6 ;.. (Ineq. set A)

Aug 31, '02VDAT'02: Low-Power Design15 Validation of the Model Buffer Constraints: T 2 = t 2 = d 2 ; T 3 = t 3 = d 3 ; (Ineq. set B) Substituting Ineq. set B in Ineq. set A t 6 – d 2 < d 6..( 1 ) t 6 – d 1 – d 3 < d 6..( 2 ) d 6 < T 6 – d 2..( 3 ) d 6 < T 6 – d 1 – d 3..( 4 )

Aug 31, '02VDAT'02: Low-Power Design16 Validation of New Model Adding ineq. ( 1 ) and ( 4 ), and using (A) d 1 + d 3 – d 2 < T 6 – t 6 < d 6 Adding ineq. ( 2 ) and ( 3 ), and using (A) d 2 – d 3 – d 1 < T 6 – t 6 < d 6 These are the same inequalities as for the old path-enumeration model. Similar derivation can be done for maxdelay constraints. Hence the new model constraints are equivalent to the old ones.

Aug 31, '02VDAT'02: Low-Power Design17 Why New Model is Superior? Path constraints from old model 4 × 4 × …4 = 4 n Constraints from new model 15 × n = 15n Hence new constraint set is linear in size of circuit.

Aug 31, '02VDAT'02: Low-Power Design18 Comparison of Constraints Number of gates in circuit Number of constraints c880 3, x10 6

Aug 31, '02VDAT'02: Low-Power Design19 Results: Procedure Outline C++ Program AMPL* Power Estimator Combinational circuit netlist Results Constraint-set Optimized delays *Fourer, Gay and Kernighan, AMPL: A Modeling Language for Mathematical Programming, 1993.

Aug 31, '02VDAT'02: Low-Power Design20 Results: 1-Bit Adder

Aug 31, '02VDAT'02: Low-Power Design21 Estimation of Power Circuit is simulated by an event-driven simulator for both optimized and un- optimized gate delays. All transitions at a gate are counted as Events[gate]. Power consumed  Events[gate] x # of fanouts. Reference: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ISLPED`97).

Aug 31, '02VDAT'02: Low-Power Design22 Original 1-Bit Adder Color codes for number of transitions

Aug 31, '02VDAT'02: Low-Power Design23 Optimized 1-Bit Adder Color codes for number of transitions

Aug 31, '02VDAT'02: Low-Power Design24 Results: 1-Bit Adder Simulated over all possible vector transitions Average power = optimized/unit delay = 244 / 308 = Peak power = optimized/unit delay = 6 / 10 = 0.60 Power Savings : Peak = 40 % Average = 21 %

Aug 31, '02VDAT'02: Low-Power Design25 Results: 4-Bit ALU maxdelayBuffers inserted Power Savings : Peak = 33 %, Average = 21 %

Aug 31, '02VDAT'02: Low-Power Design26 Power Dissipation of ALU4 Energy in nanojoules microseconds Original ALU delay ~ 3.5ns Minimum energy ALU delay ~ 10ns 1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random vectors simulated in Spice

Aug 31, '02VDAT'02: Low-Power Design27 Benchmark Circuits Circuit C432 C880 C6288 c7552 Maxdel. (gates) No. of Buffers Average Peak Normalized Power

Aug 31, '02VDAT'02: Low-Power Design28 Conclusion Obtained an LP constraint-set that is linear in the size of the circuit. LP solution: Eliminates glitches at all gate outputs, Holds I/O delay within specification, and Combines path-balancing and hazard-filtering to minimize the number of delay buffers. New LP produces results exactly identical to old LP requiring exponential constraint-set. Results show peak power savings up to 40% and average power savings up to 21%.