1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5) Date: 3/8/2006 Functional Block Layout / Floorplan Design Manager: Abhishek Jajoo

2Status  Design Proposal  Project chosen: 16 bit Delta-Sigma ADC  Basic specs defined  Architecture  Matlab Simulated  Behavioral Verilog - Simulated  Structural Verilog – Simulated  Schematic  Digital – All modules created  Analog - All modules created  Floorplan  Adjusted floorplan based on layouts  Layout  Moving forward with bit-sliced sinc filter and other digital parts  Beginning analog layout  Putting it all together  Simulation / Verification  All modules verified separately at transistor level

3 Design Decisions Now using different topologies for integrating and comparing opamps Now using different topologies for integrating and comparing opamps Using nwell resistors and poly/metal1/metal2/metal3 capacitors Using nwell resistors and poly/metal1/metal2/metal3 capacitors Higher resistance / capacitance reduces area Higher resistance / capacitance reduces area

4 Algorithm Detail Decimation (Sinc Filter, Downsample) Measure Peak Amplitude (Peak Input Indicator) Digital Output Digital Peak Indicator Analog Input Lowpass Filter Analog to Digital Conversion (Delta-Sigma Modulator) Analog

5 Digital Progress Sinc filter bitslice is progressing nicely Sinc filter bitslice is progressing nicely Other main blocks laid out, DRC’d and LVS’d Other main blocks laid out, DRC’d and LVS’d Extracted cells’ performance match schematics’ as well as expected Extracted cells’ performance match schematics’ as well as expected You’ll hear more of these details next time... You’ll hear more of these details next time...

6 Low Pass Filter Helps prevent high frequency signals from entering the modulator Helps prevent high frequency signals from entering the modulator Aliasing occurs when sampling rate isn’t high enough to properly capture signals, and output is dirtied Aliasing occurs when sampling rate isn’t high enough to properly capture signals, and output is dirtied Sampling rate is fixed in our design Sampling rate is fixed in our design (20 KHz), so we need to keep input signals below 10KHz to prevent aliasing (remember the Nyquist rate?)

7 Filter Topology We’re using a 1 st order, differential Butterworth filter: We’re using a 1 st order, differential Butterworth filter:

8 Filter Layout Uses nwell resistors and sandwiches of poly and metal for capacitors, and res_id and cap_id for proper extraction: Uses nwell resistors and sandwiches of poly and metal for capacitors, and res_id and cap_id for proper extraction: Pictures taken from slides

9 Filter Layout (cont.)

10 Modulator Basics

11 Opamp Design Integrating opamp needs some gain, high speed, moderate slew rate, differential inputs and outputs Integrating opamp needs some gain, high speed, moderate slew rate, differential inputs and outputs Comparing opamp needs high gain, high speed, high slew rate, differential inputs and single ended output Comparing opamp needs high gain, high speed, high slew rate, differential inputs and single ended output Doesn’t make sense to use the same design for both! Doesn’t make sense to use the same design for both!

12 Balancing Design Parameters Gain Robustness Speed / Bandwidth Power Area The Perfect Design (??)

13 Integrating Opamp Topology

14 Comparator Topology

15 Putting It All Together When we simulate this: When we simulate this:

16 Putting It All Together (cont.) We get this: We get this:

17 How It All Adds Up… Total = 14,441 transistors, uW of power BlockPowerDelayTransistors 16-Bit Adder22.47uW at 5.12MHz2.856ns Bit Subtractor28.54uW at 5.12MHz 13.09uW at 20KHz 2.916ns Bit Register22.41uW at 20KHz1.065ns Bit Register33.17uW at 5.12MHz 29.88uW at 20KHz 1.065ns Bit Equality Function3.323uW at 20KHz270.5ps Bit Multiplexer2.114uW at 20KHz24.7ps96 Clock Divider4.812uW241.5ps334 2nd order Sinc Filter227.1uW8.748ns3296 PII Function115.9uW2.950ns2782 Decimator347.8uW8.748ns6412 Analog Op-Amps162uW Total (81 uW each) N/A11 for Integrator, 9 for Comparator

18Floorplan  Essentially the same as last week  Layout hasn’t been too different from schematic… (yet)

19 Problems and Questions Still have the same problem with top level simulation Still have the same problem with top level simulation Its just impractically slow… Its just impractically slow… Increase gain of integrator? Increase gain of integrator? Lowers area of passive elements in modulator Lowers area of passive elements in modulator Increases power and/or area, and our headaches Increases power and/or area, and our headaches Strange Cadence behavior Strange Cadence behavior