HV for SM surface testing 2 nd Workshop on the Detector Control System for TRD University of Tsukuba Kengo Watanabe

2 Status Iseg HV ・ Drift: 4 modules with 8 channels each ・ Anode: 1 module with 32 channels (Two independent modules with 16 channels) ・ Communication between devices and client has been established FSM ・ Standard HV state diagram plus error state implemented ・ Panels for detector oriented nodes are ready

3 Iseg HV Operation by PVSS ・ Iseg OPC server can communicate to Iseg devices ・ PVSS can communicate to Iseg devices through the Iseg OPC server Available data points ・ Set and monitor the state of device’s power ・ Set and monitor the voltage and the current values ・ Monitor the ramping and the trip state

4 Standard HV state diagram For stack and topFor channel and layer

5 TRD HV top panel FSM State Indicator Simple monitoring panel open Recipe Value Crate Control Module setting panel

6 Simple monitoring Panel For Drift For Anode

7 Single Channel Panel FSM State Indicator Voltage and current indicator Setting Panel Trending monitor

8 Planning Improve ramping state behavior ・ Automatic chamber conditioning algorithm ex. Stop ramping near the trip value Fix some FSM instabilities ・ Unexpected states show up from time to time Integrate into main DCS project (Jorge) Install HV project to Munster