ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 1 Automatic Die Placement and Flexible I/O Assignment in 2.5D IC Design Daniel P. Seemuth Prof. Azadeh Davoodi Prof. Katherine Morrow University of Wisconsin – Madison Dept. of Electrical and Computer Engineering

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 2 Background: 2.5D Integrated Circuits Provides potential to assemble dies from multiple vendors together on a single 2.5D IC

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 3 Motivation Designing 2.5D embedded systems and integrated circuits is complicated! – Necessitates abstraction and computer-aided design Opportunity: some of the connections between dies may have flexibility in pin assignments – FPGAs with flexible pins – General-purpose I/Os (GPIOs) Flexible interconnect increases design freedom, but also search space – Gives the potential for better solutions – But… need to FIND those solutions!

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 4 Motivation Challenge: placement and pin assignment decisions are inter-related! Pin assignment affects the best placement Placement affects the best pin assignment

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 5 2.5D IC Design Automation Goal: allow designer to specify connectivity requirements without limiting flexibility Created a 2.5D IC design framework – Designer specifies design requirements: Component dies Net names, I/O standards, eligible pins – Framework simultaneously performs: Die placement Bank voltage supply assignment Pin assignment Framework takes advantage of flexible interconnect to find improved solutions

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 6 Simulated Annealing Implementation Simulated annealing (SA): “guided” random movement through solution space – Move (translate) a die – Rotate a die – Swap two dies’ positions – Reassign a net to a different eligible pin Start at “high temperature” – All “good” moves and many “bad” moves accepted Decrease temperature as algorithm progresses – All “good” moves still accepted – Probability of accepting a “bad” move decreases

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 7 Simulated Annealing Implementation Moves per temperature based on # of dies and # of nets in problem – Automatically tunes simulated annealing based on the problem size Probability of making a die vs. net move based on the proportion of each move type remaining Cooling process: – Based on VPR’s cooling schedule – Fast cooling at extreme temperatures, slower for a good balance of accepted vs. rejected moves Parameter details given in the paper…

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 8 Simulated Annealing Cost Function Direct costs 1.Average half-perimeter wirelength (HPWL) 2.Maximum HPWL 3.Layout bounding-box area Penalties for hard constraints 4.Dimensions > maximum 5.Die overlap 6.Pins incompatible with power supplies 7.Connection oversubscription Constant weights Weight ↑ as T↓

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 9 2.5D Placement & Pin Assignment Simulated annealing phase produces: – Position for each die – Voltage for each bank’s power supply – Pins for each connection SA may find pin assignment close to ideal Perform final pin refinement step after SA – Uses ILP formulation to: Minimize total wirelength Meet all physical requirements Meet connectivity requirements – Improved wirelength by small factor

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 10 Comparison Methodology Compare simultaneous method with sequential method (placement, then pin assignment) Sequential method: – Place dies using simulated annealing Same parameters as simultaneous SA method Use die center as estimated connection endpoint, since pin assignments not yet made – Assign pins using ILP formulation Comparable formulation used for pin refinement for simultaneous method

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow D Results: Placement First Using center of each die to approximate endpoint location leads to inaccurate wirelength estimates

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow D Results: Simultaneous P & PA Wirelength estimates more accurate when based on actual pin assignment Layout improves when pin assignment is updated based on placement and vice-versa

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow D Results Comparison Placement and pin assignment inter-related Improve results with simultaneous placement and pin assignment Placement, then pin assignment HPWL: mm Area: mm 2 Simultaneous placement and pin assignment HPWL: mm (- 51%) Area: mm 2 (+ 2.5%)

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow D Results: Larger System Placement, then pin assignment HPWL: mm Area: mm 2 Simultaneous placement and pin assignment HPWL: mm (- 40%) Area: mm 2 (+ 16%)

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow D Results Summary Simultaneous placement and pin assignments improves layout quality – Significant improvements to HPWL – Small area penalty Avg costs over 10 solutions for each method: SystemMethodTotal HPWL Interposer Area Five-die Sequential2837 mm236.2 mm 2 Simultaneous1530 mm252.6 mm 2 Ring Sequential10435 mm711.2 mm 2 Simultaneous6876 mm804.9 mm 2

ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 16 Conclusion Proposed method accommodates flexible interconnect in 2.5D IC design automation – Die placement – Bank power supply voltage assignment – Pin and differential pair assignment More effective than separately performing placement followed by pin assignment – Significantly improved wirelength at only a small cost in area