Notes on the ez430-RF2500

Sources

Gotchas int: 2 bytes, default: signed, to WDTCTL = WDTPW + WDTHOLD;

Operators ~A A | B A & B A ^ B A |= B A &= ~B A ^=B A=A<<2;

Clocks Clocks: LFXT1CLK (Low Frequency Crystal Clock), external DCO (Digitally Controlled Oscillator), stable in less than 2us at 1MHz. – BCSCTL1-RSELx[3-0]: frequency range – DCOCTL-DCOx[7-5]: frequency inside a given range – DCOCTL-MODx[4-0]: modulator VLOCLK (Very low power, low frequency oscillator), internal, 12kHz – Replaces LFXT1CLK when BCSCTL3-LFXT1Sx[5-4]=0b10 or 0b11 and BCSCTL1-XTS[6]=0 – Don’t forget to clear the OFIFG flag (IFG1 &= ~0x02), make sure it remains cleared Clock lines: MCLK (Master Clock) for CPU, default on DCO – BCSCTL2-SELMx[7-6]: select source – BCSCTL2-DIVMx[5-4]: divider – SR-CPUOFF[4]: turn on/off SMCLK (Submaster Clock) for peripherals, default on DCO – BCSCTL2-SELS [3]: select source – BCSCTL2-DIVSx[2-1]: divider – SR:SCGx [7-6]: turn on/off ACLK, always on LFXTCLK, used for interrupts – BCSCTL1-DIVAx[5-4]: divider

Registers PxDIR (x=1,2,3,4) PxIN PxOUT PxSEL (select role of the register) SR (Status Register), for branching Basic Clock System Control Register 2 (BCSCTL2)

Interrupt Flags PORIFG: Power On Reset RSTIFG: Reset Reset vector at 0xFFFE points to 0x8000

Interrupts Interrupt priorities 8 - non-maskable: External Reset, Power-up, Watchdog Timer Reset, Flash Key Violation, NMI 7 - non-maskable: Oscillator Fault, Flash Memory Access Violation 6 - maskable: Watchdog Timer 5 - maskable: Timer A Capture Compare Register 0 (CCR0) interrupt 4 - maskable: Timer A Capture Compare Register 1 (CCR1) Interrupt 3 - maskable: Sigma/Delta 16 bit (SD16) Converter Interrupt 2 - maskable: Universal Serial Interface (USI) Interrupts 1 - maskable: Port 2 I/O Interrupts 0 - maskable: Port 1 I/O Interrupts Steps to execute interrupt (6 cycles) 1.PC to stack 2.SR to stack 3.Highest priority interrupt selected 4.IFL reset for single source interrupts only 5.SR cleared, except SR-SCG0 (no LPM, no GIE) 6.Interrupt vector to PC Steps to leave interrupt (5 cycles) Pop stack to SR Pop stack to PC

SR, Status Register __bix_SR_register __get_SR_register __bix_SR_register_on_exit __get_SR_register_on_exit

LEDS (red:P1.0, green :P1.1) Direction P1DIR |= 0x03; On P1OUT |= 0x01; Off P1OUT &= ~0x01; Toggle P1OUT ^= 0x01;

Low Power Modes

Addressing Modes

Instructions

Timer_A

Timer_B

USI

USCI

ADC10