1. Instructor: Dr Aleksandar Milenkovic Lecture Notes
CPE 323 Introduction to Embedded Computer Systems: The MSP430 System Architecture
Instructor: Dr Aleksandar Milenkovic Lecture Notes
Alex Milenkovich

2. MSP430: System Architecture
Outline
MSP430: System Architecture
System Resets, Interrupts, and Operating Modes
Basic Clock Module
Watchdog Timer
CPE 323
Alex Milenkovich

3. MSP430: System Resets, Interrupts, and Operating Modes
Alex Milenkovich

4. Resets
Reset – a sequence of operations that put device into a well-defined state (from which the user’s program may start)
Performed when
Power is first applied and
Device detects serious fault in hardware or software from which the user’s program cannot be expected to recover
MSP430 supports two types of reset (HW and SW controlled)
Power-on Reset (POR)
Power-up Clear (PUC)
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5. Power-on Reset (POR)
Generated by the following severe conditions related to hardware
Device is powered-up. POR us raised if the supply voltage drops to so low a value that the device may not work correctly. Include brownout detector.
A low external signal on the #RST/NMI pin (if the pin is configured for the reset function rather than the nonmaskable interrupt). Active by default
Some MSP430s have a more comprehensive supply voltage supervisor (SVS). It sets the SVSFG flag if the voltage falls below the programmed level and can optionally reset the device
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6. Power-Up Clear (PUC)
It always follows the POR. It is generated when software appears to be out of control
Watchdog time overflows in watchdog mode
Write into the watchdog control register (WDTCTL) with incorrect password in the upper byte. Can be triggered even if the WDT is disabled or operates in the interval mode
Correct password is 0x5A available as symbol WDTPW
Write an incorrect password into the flash memory controller registers (FCTLn)
Protects the stored program from a runaway software
In newer devices, a PUC is triggered when we try to fetch an instruction from the range of addresses reserved for peripheral I/O or for unimplemented memory
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7. System Reset Power-up Clear Power-on Reset (POR) A POR signal
Powering up the device
A low signal on the RST/NMI pin when configured in the reset mode
An SVS low condition when PORON=1.
Power-up Clear
A POR signal
Watchdog timer expiration when in watchdog mode only
Watchdog timer security key violation
A Flash memory security key violation
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Alex Milenkovich

8. Power-On Reset (POR)
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9. Brownout Reset
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10. Conditions after Reset
Initial conditions for all registers and peripherals after POR and PUC are specified in the family’s user guides; some common effects
#RST/NMI pin is configured for reset
Most I/O pins are configured as digital inputs
For registers see the manual. Notation is as follows
rw-0: means that a bit can be read and written and is initialized to 0 after a PUC
rw-(0): means that a bit can be read and written and is initialized to 0 after a POR and retains its value after a PUC
Status register is cleared (R2=0): active mode
WDT starts in watchdog mode
PC is loaded with the reset vector which
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11. Reset related flags
How to identify a source of the reset when debugging
IFG – Interrupt Flag Register (IFG1, IFG2)
WDTIFG: shows that the WDT timed out or its security key is violated
OFIFG: indicates an oscillator fault (causes a nonmaskable interrupt, not reset)
RSTIFG: indicates a reset caused by a signal on the #RST/NMI pin
PORIFG: is set on power-on reset
NMIIFG: flags a non-maskable interrupt caused by a signal on #RST/NMI
These bits are not cleared by a PUC, so they can be tested to identify the source of the PUC
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12. Software configuration
Your SW must configure the MSP430
Initialize the SP, typically to the top of RAM
Configure the watchdog to the requirements of the application
Setup the clock (clocks)
Configure all ports (unused pins should never be left as floating inputs).
Configure peripheral modules to the requirements of the application (e.g. TimerA, ADC12, ...)
Finally enable interrupts if needed
Note: Additionally, the watchdog timer, oscillator fault, and flash memory flags can be evaluated to determine the source of the reset
CPE 323
Alex Milenkovich

13. Exceptions/Interrupts (CHAPTER 6 in Textbook)
Events caused by hardware or software that require an urgent response
E.g., a packet of data has been received, a new sample from ADC is ready, etc.
What do we need when an interrupt request is raised
Processor stops its current task
Stores enough information to be able to resume the task later (PC and SR)
Executes an Interrupt Service Routine (ISR) or Interrupt Handler
Like a subroutine to handle a specific request. It can be invoked at hardware at UNPREDICTABLE times
Exception processing
What are possible sources of interrupt requests (HW internal/external, SW)?
What do we do in presence of multiple requests?
How do we decide which request to accept (priorities, masking, selective masking)?
Where do we find the starting address of an ISR (vector table)
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14. When Do We Use Interrupts
Crucial in embedded systems – tasks are often triggered by external events
Handle urgent tasks that need to be executed at higher priority than the main code
E.g., a received data packet should be read from a communication devices before it gets overwritten by another one
Handle infrequent tasks
E.g., reading slow input devices (key pressed). An alternative is I/O polling – CPU waits for an event – would be extremely inefficient
Wake the CPU from sleep
CPU is in a low-power mode to conserve energy
Calls to an operating system (SW interrupt)
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15. Interrupt Service Routines
Look like a subroutine
Unique characteristics:
Interrupts arise at unpredictable times and require prompt response =>
ISR is carried out in such a way to allow the main code to resume without any error (like it has never occurred)
Triggered by events in the CPU, peripherals, busses (hardware) or software (interrupt instruction)
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16. Tracking Interrupts and Masking
Interrupt Flags
Each interrupt has a flag
E.g., TAIFG – Timer A Interrupt Flag
It is set when a the condition for interrupt occur
Can be read from SW at any time (polling)
Cleared when an interrupt is accepted
by HW automatically in case of single-sourced interrupts
by SW in the ISR in case of multiple-sourced interrupts
Maskable Interrupts
Each flag has a corresponding enable bit
E.g, TAIE – Timer A Interrupt Enable
Allows us to selectively enable/disable interrupts
GIE – General Interrupt Enable in SR; when cleared all MASKABLE interrupt requests are ignored; non-maskable are not affected (though they may have their own mask bits)
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17. Interrupt Vector Table
Address of an ISR (vector) is stored in a table – interrupt vector table
Starts at defined address in memory
Vector is determined based on the source of the interrupt
Single sourced interrupts: each vector is associated with a unique interrupt
Multi-sourced interrupts: multiple sources may share a single vector
Priority: each vector has a distinct priority
Defines which vector is taken if more than one request exists
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18. MSP430 Interrupts
3 types
System reset
(Non)-maskable NMI
Maskable
Interrupt priorities are fixed and defined by the arrangement of modules
CPE 323
Alex Milenkovich

19. (Non)-Maskable Interrupts (NMI)
Sources
An edge on the RST/NMI pin when configured in NMI mode
An oscillator fault occurs
An access violation to the flash memory
Are not masked by GIE (General Interrupt Enable), but are enabled by individual interrupt enable bits (NMIIE, OFIE, ACCVIE)
CPE 323
Alex Milenkovich

20. NMI Interrupt Handler
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21. What Happens When an Interrupt Is Requested?
1) Any currently executing instruction is completed.
2) The PC, which points to the next instruction, is pushed onto the stack.
3) The SR is pushed onto the stack.
4) The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service.
5) The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set for servicing by software.
6) The SR is cleared with the exception of SCG0, which is left unchanged. This terminates any low-power mode. Because the GIE bit is cleared, further interrupts are disabled.
7) The content of the interrupt vector is loaded into the PC: the program continues with the interrupt service routine at that address.
Takes 6 cc to execute
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Alex Milenkovich

22. What Happens on Return from Interrupt?
RETI - Return from Interrupt Service Routine
1) The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are now in effect, regardless of the settings used during the interrupt service routine.
2) The PC pops from the stack and begins execution at the point where it was interrupted.
Takes 5 cc to execute
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23. Interrupt Vectors
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24. Interrupt Vectors
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
#define PORT2_VECTOR * 2 /* 0xFFE2 Port 2 */
#define UART1TX_VECTOR * 2 /* 0xFFE4 UART 1 Transmit */
#define UART1RX_VECTOR * 2 /* 0xFFE6 UART 1 Receive */
#define PORT1_VECTOR * 2 /* 0xFFE8 Port 1 */
#define TIMERA1_VECTOR * 2 /* 0xFFEA Timer A CC1-2, TA */
#define TIMERA0_VECTOR * 2 /* 0xFFEC Timer A CC0 */
#define ADC_VECTOR * 2 /* 0xFFEE ADC */
#define UART0TX_VECTOR * 2 /* 0xFFF0 UART 0 Transmit */
#define UART0RX_VECTOR * 2 /* 0xFFF2 UART 0 Receive */
#define WDT_VECTOR * 2 /* 0xFFF4 Watchdog Timer */
#define COMPARATORA_VECTOR 11 * 2 /* 0xFFF6 Comparator A */
#define TIMERB1_VECTOR * 2 /* 0xFFF8 Timer B 1-7 */
#define TIMERB0_VECTOR * 2 /* 0xFFFA Timer B 0 */
#define NMI_VECTOR * 2 /* 0xFFFC Non-maskable */
#define RESET_VECTOR * 2 /* 0xFFFE Reset [Highest Pr.] */
CPE 323
Alex Milenkovich

25. Interrupt Service Routines
ASM EXAMPLE
Reset: MOV.W #SFE(CSTACK),SP ; main program
....
JMP $ ; loop forever
TA0_ISR: ... ; ISR
RETI ; return from interrupt ;
COMMON INTVEC ; segment for vectors
ORG TIMERA_VECTOR
DW TA0_ISR ; ISR for TimerA
ORG RESET_VECTOR ; address to start ex.
DW Reset
END
C EXAMPLE
#pragma vector = TIMERA0_VECTOR
__interrupt void TA0_ISR (void){
// ISR code }
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Alex Milenkovich

26. Operating Modes (to be discussed later)
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27. MSP430: Clock System
Alex Milenkovich

28. Clock System: An Introduction
Clock – square wave whose edges trigger hardware
Traditional clocks: a crystal with frequency of a few MHz is connected to two C pins; internally the clock may be divided by 2 or 4.
Typical application cycle in embedded systems
C stays in a low-power mode until
An event wakes up C to handle it
Often need multiple clocks (fast for CPU, slow for peripherals)
Power consumption: P ~ CV2f
CPE 323
Alex Milenkovich

29. Clock System: An Introduction
Crystal clocks
Accurate (the frequency is typically within 11 part in 100,000), stable (do not change with time or temperature)
High-frequency (a few MHz) or low-frequency (32,768 Hz) for a real-time clock
Expensive, delicate, draw a relatively large current, require additional components (capacitors), take long time to start up and stabilize
Resistor and capacitor (RC) clocks
Cheap, quick to start
Poor accuracy and stability
Can be external or integrated into a chip
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Alex Milenkovich

30. MS430 Clock System
Flexible to address conflicting demands for high-performance, low-power, and a precise frequency
3 internal clocks from 4 possible sources: MCLK, SMCLK, ACLK
Master clock, MCLK: used by the CPU and a few peripherals (e.g., ADC12, DMA, ...)
Subsystem master clock, SMCLK: distributed to peripherals
Auxiliary clock, ACLK: distributed to peripherals
Typical configuration: MCLK and SMCLK are in the megahertz range, ACLK is 32 KHz
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31. Clock System: MSP430
Digitally controlled Oscillator, DCO: available in all devices; highly-controllable oscillator
Generated on-chip RC-type frequency controlled by SW + HW
Low- or high-frequency crystal oscillator, LFXT1
LF: 32768Hz
XT: 450kHz MHz
High-frequency crystal oscillator, XT2
Internal very low-power, low-frequency oscillator, VLO: available in more recent MSP430F2xx devices; provides an alternative to LFXT1 when accuracy is not needed
CPE 323
Alex Milenkovich

32. Basic Clock System: MSP430x1xx
DCOCLK Generated on-chip with 6s start-up
32KHz Watch Crystal - or - High Speed Crystal / Resonator to 8MHz
(our system is 4MHz/8MHz high Speed Crystal)
Flexible clock distribution tree for CPU and peripherals
Programmable open-loop DCO Clock with internal and external current source
LFXT1 oscillator
32kHz
8MHz
XIN
LFXT1CLK
ACLK
Auxiliary Clock
to peripherals
XOUT
LFXT2CLK
Clock
Distribution
MCLK
Main System Clock
to CPU
100kHz - 5MHZ
Digital Controlled Oscillator
DCO
DCOCLK
Rosc
SMCLK
Sub-System Clock
to peripherals
CPE 323
Alex Milenkovich

33. Basic Clock System – Block Diagram
DIVA 2
LFXTCLK
ACLK
/1, /2, /4, /8
OscOff
XTS
Auxiliary Clock
ACLKGEN
SELM
DIVM
CPUOff
High frequency 2 2
XT oscillator, XTS=1 3
0,1
MCLK
/1, /2, /4, /8, off
Low power 2
MCLKGEN
Main System Clock
Vcc
LF oscillator, XTS=0
Vcc
Rsel
SCG0
DCO
MOD
SELS
DIVS
SCG1 3 5
DCOCLK 2
DC-
Digital Controlled Oscillator DCO
SMCLK +
/1, /2, /4, /8, off
Generator 1
Modulator MOD
P2.5
/Rosc 1
Sub-System Clock
DCOR
DCGEN
DCOMOD
SMCLKGEN
The DCO-Generator is connected to pin P2.5/Rosc if DCOR control bit is set.
The port pin P2.5/Rosc is selected if DCOR control bit is reset (initial state).
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34. Basic clock block diagram (MSP430x13x/14x/15x/16x)
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35. Basic operation
After POC (Power Up Clear) MCLK and SMCLK are sourced by DCOCLK (approx. 800KHz) and ACLK is sourced by LFXT1 in LF mode
Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure the MSP430 operating modes and enable or disable portions of the basic clock module
SCG1 - when set, turns off the SMCLK
SCG0 - when set, turns off the DCO dc generator (if DCOCLK is not used for MCLK or SMCLK)
OSCOFF - when set, turns off the LFXT1 crystal oscillator (if LFXT1CLK is not use for MCLK or SMCLK)
CPUOFF - when set, turns off the CPU
DCOCTL, BCSCTL1, and BCSCTL2 registers configure the basic clock module
The basic clock can be configured or reconfigured by software at any time during program execution
CPE 323
Alex Milenkovich

36. Basic Clock Module - Control Registers
The Basic Clock Module is configured using control registers DCOCTL, BCSCTL1, and BCSCTL2, and four bits from the CPU status register: SCG1, SCG0, OscOff, and CPUOFF.
User software can modify these control registers from their default condition at any time. The Basic Clock Module control registers are located in the byte-wide peripheral map and should be accessed with byte (.B) instructions.
Register State Short Form Register Type Address Initial State
DCO control
register DCOCTL Read/write 056h 060h
Basic clock
system control BCSCTL Read/write 057h 084h
system control BCSCTL Read/write 058h reset
CPE 323
Alex Milenkovich

37. Basic Clock Module - Control Registers
rw-0
SELM.1
058h
BCSCTL2
SELM.0
DIVM.1
DIVM.0
SELS
DIVS.1
DIVS.0
DCOR
Direct SW Control
DCOCLK can be Set - Stabilized
Stable DCOCLK over Temp/Vcc.
rw-(1)
rw-(0)
rw-0
rw-1
057h
BCSCTL1
XT2Off
Rsel.0
Rsel.1
Rsel.2
XTS
DIVA.1
DIVA.0
XT5V
rw-0
rw-1
DCO.2
056h
DCOCTL
DCO.1
DCO.0
MOD.4
MOD.3
MOD.2
MOD.1
MOD.0
Selection of DCO nominal frequency
Which of eight discrete DCO frequencies is selected
Define how often frequency fDCO+1 within the period of 32 DCOCLK cycles is used. Remaining clock cycles (32-MOD) the frequency fDCO is mixed
RSEL.x Select DCO nominal frequency
DCO.x and MOD.x set exact DCOCLK
… select other clock tree options
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Alex Milenkovich

38. DCOCTL
Digitally-Controlled Oscillator (DCO) Clock-Frequency Control
DCOCTL is loaded with a value of 060h with a valid PUC condition.
DCOCTL DCO.2 DCO.1 DCO.0 MOD.4 MOD.3 MOD.2 MOD.1 MOD.0
056H
MOD.0 .. MOD.4: The MOD constant defines how often the discrete frequency fDCO+1 is used within a period of 32 DCOCLK cycles.
During the remaining clock cycles (32–MOD) the discrete frequency f DCO is used. When the DCO constant is set to seven, no modulation is possible since the highest feasible frequency has then been selected.
DCO.0 .. DCO.2: The DCO constant defines which one of the eight discrete frequencies is selected. The frequency is defined by the current injected into the dc generator.
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39. BCSCTL1 Oscillator and Clock Control Register
BCSCTL1 is affected by a valid PUC or POR condition.
BCSCTL1 XT2Off XTS DIVA.1 DIVA.0 XT5V Rsel.2 Rsel.1 Rsel.0
057h
Bit0 to Bit2: The internal resistor is selected in eight different steps.
Rsel.0 to Rsel.2 The value of the resistor defines the nominal frequency.
The lowest nominal frequency is selected by setting Rsel=0.
Bit3, XT5V: XT5V should always be reset.
Bit4 to Bit5: The selected source for ACLK is divided by:
DIVA = 0: 1
DIVA = 1: 2
DIVA = 2: 4
DIVA = 3: 8
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Alex Milenkovich

40. BCSCTL1
Bit6, XTS: The LFXT1 oscillator operates with a low-frequency or with a high-frequency crystal:
XTS = 0: The low-frequency oscillator is selected.
XTS = 1: The high-frequency oscillator is selected.
The oscillator selection must meet the external crystal’s operating condition.
Bit7, XT2Off: The XT2 oscillator is switched on or off:
XT2Off = 0: the oscillator is on
XT2Off = 1: the oscillator is off if it is not used for MCLK or SMCLK.
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41. BCSCTL2 BCSCTL2 SELM.1 SELM.0 DIVM.1 DIVM.0 SELS DIVS.1 DIVS.0 DCOR
BCSCTL2 is affected by a valid PUC or POR condition.
BCSCTL2 SELM.1 SELM.0 DIVM.1 DIVM.0 SELS DIVS.1 DIVS.0 DCOR
058h
Bit0, DCOR: The DCOR bit selects the resistor for injecting current into the dc generator. Based on this current, the oscillator operates if activated.
DCOR = 0: Internal resistor on, the oscillator can operate. The fail-safe mode is on.
DCOR = 1: Internal resistor off, the current must be injected externally if the DCO output drives any clock using the DCOCLK.
Bit1, Bit2: The selected source for SMCLK is divided by:
DIVS.1 .. DIVS DIVS = 0:1
DIVS = 1: 2
DIVS = 2: 4
DIVS = 3: 8
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Alex Milenkovich

42. BCSCTL2 or Bit3, SELS: Selects the source for generating SMCLK:
SELS = 0: Use the DCOCLK
SELS = 1: Use the XT2CLK signal (in three-oscillator systems) or
LFXT1CLK signal (in two-oscillator systems)
Bit4, Bit5: The selected source for MCLK is divided by DIVM.0 .. DIVM.1
DIVM = 0: 1
DIVM = 1: 2
DIVM = 2: 4
DIVM = 3: 8
Bit6, Bit7: Selects the source for generating MCLK:
SELM.0 .. SELM.1
SELM = 0: Use the DCOCLK
SELM = 1: Use the DCOCLK
SELM = 2: Use the XT2CLK (x13x and x14x devices)
Use the LFXT1CLK (x11x(1) devices)
SELM = 3: Use the LFXT1CLK
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43. Range (RSELx) and Steps (DCOx)
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44. F149 default DCO clock setting
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slas272c/page 46
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45. External Resistor
The DCO temperature coefficient can be reduced by using an external resistor ROSC to source the current for the DC generator.
ROSC also allows the DCO to operate at higher frequencies.
Internal resistor nominal value is approximately 200 kOhm => DCO to operate up to 5 MHz.
External ROSC of approximately 100 kOhm => the DCO can operate up to approximately 10 MHz.
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46. Basic Clock Systems-DCO TAPS
DCOCLK frequency control
nominal - injected current into DC generator
1) internal resistors Rsel2, Rsel1 and Rsel0
2) an external resistor at Rosc (P2.5/11x)
Control bits DCO0 to DCO2 set fDCO tap
Modulation bits MOD0 to MOD4 allow
mixing of fDCO and fDCO+1 for precise
frequency generation f 1 2 3 4 5 6 7
DCOCLK
fDCO
nominal
nominal+1
Selected
nominal-1
Example Selected:
f3:
f4:
1000kHz
943kHz
1042kHz
Frequency
Cycle time
1000 nsec
1060 nsec
960 nsec
MOD=19
DCOCLK
DCO +0 +1
Modulation Period
To produce an intermediate effective frequency between fDCO and fDCO+1
Cycle_time = ((32-MOD)*tDCO+MOD*tDCO+1)/32 = ns, selected frequency  1 MHz.
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47. Software FLL Basic Clock DCO is an open loop - close with SW+HW
A reference frequency e.g. ACLK or 50/60Hz can be used to measure DCOCLK’s
Initialization or Periodic software set and stabilizes DCOCLK over reference clock
DCOCLK is programmable 100kHz - 5Mhz and stable over voltage and temperature
Digital Controlled Oscillator DCO +
DCO 3
DCOMOD
MOD 5
Modulator MOD
DCOCLK
Vcc
DCOR 1
P2.5
/Rosc
DC-
Generator
SCG0
Rsel
DCGEN
reference clock e.g.
ACLK or 50/60Hz
SW+HW
Controls the DCOCLK
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48. Software FLL Implementation
Example: Set DCOCLK= , ACLK= 32768
ACLK/4 captured on CCI2B, DCOCLK is clock source for Timer_A
Comparator2 HW captures SMCLK ( Hz) in one ACLK/4 (8192Hz) period
Target Delta = /8192= 150
CCI2BInt … ; Compute Delta
cmp #150,Delta ; Delta= /8192
jlo IncDCO ; JMP to IncDCO
DecDCO dec &DCOCTL ; Decrease DCOCLK
reti
IncDCO inc &DCOCTL ; Increase DCOCLK 15
Capture/Compare 1 2 3
Register CCR2
CCI2B
Capture
Mode
Comparator 2
Target Hz DCOCLK source for timer
Stable reference ACLK/4, 8192Hz source
Delta
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49. Fail Safe Operation
Basic module incorporates an oscillator-fault detection fail-safe feature.
The oscillator fault detector is an analog circuit that monitors the LFXT1CLK (in HF mode) and the XT2CLK.
An oscillator fault is detected when either clock signal is not present for approximately 50 us.
When an oscillator fault is detected, and when MCLK is sourced from either LFXT1 in HF mode or XT2, MCLK is automatically switched to the DCO for its clock source.
When OFIFG is set and OFIE is set, an NMI interrupt is requested. The NMI interrupt service routine can test the OFIFG flag to determine if an oscillator fault occurred. The OFIFG flag must be cleared by software.
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50. Synchronization of clock signals
When switching MCLK and SMCLK from one clock source to another => avoid race conditions
The current clock cycle continues until the next rising edge
The clock remains high until the next rising edge of the new clock
The new clock source is selected and continues with a full high period
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51. Basic Clock Module - Examples
How to select the Crystal Clock
BCSCTL1 |= XTS; // ACLK = LFXT1 = HF XTAL
BCSCTL1 |= DIVA0; // ACLK = XT1 / 8
BCSCTL1 |= DIVA1;
do {
IFG1 &= ~OFIFG; // Clear OSCFault flag from SW
for (i = 0xFF; i > 0; i--); // Time for flag to set by HW
} while ((IFG1 & OFIFG)); // OSCFault flag still set?
// clock is stable
BCSCTL2 |= SELM_3; // MCLK = LFXT1 (safe)
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52. Basic Clock Systems-Examples
Adjusting the Basic Clock
The control registers of the Basic Clock are under full software control. If clock
requirements other than those of the default from PUC are necessary, the Basic
Clock can be configured or reconfigured by software at any time during program
execution.
ACLKGEN from LFXT1 crystal, resonator, or external-clock source and divided by 1, 2, 4, or 8. If no LFXTCLK clock signal is needed in the application, the OscOff bit should be set in the status register.
SCLKGEN from LFXTCLK, DCOCLK, or XT2CLK (x13x and x14x only) and divided by 1, 2, 4, or 8. The SCG1 bit in the status register enables or disables SMCLK.
MCLKGEN from LFXTCLK, DCOCLK, or XT2CLK (x13x and x14x only) and divided by 1, 2, 4, or 8. When set, the CPUOff bit in the status register enables or disables MCLK.
DCOCLK frequency is adjusted using the RSEL, DCO, and MOD bits. The DCOCLK clock source is stopped when not used, and the dc generator can be disabled by the SCG0 bit in the status register (when set).
The XT2 oscillator sources XT2CLK (x13x and x14x only) by clearing the XT2Off bit.
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Alex Milenkovich

53. FLL+ Clock Module (MSP430x4xx)
FLL+ clock module: frequency-locked loop clock module
Low system cost
Ultra-low power consumption
Can operate with no external components
Supports one or two external crystals or resonators (LFXT1 and XT2)
Internal digitally-controlled oscillator with stabilization to a multiple of the LFXT1 watch crystal frequency
Full software control over 4 output clocks: ACLK, ACLK/n, MCLK, and SMCLK
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54. MSP430x43x, MSP430x44x and MSP430x461x Frequency-Locked Loop
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55. FLL+ Clock Module
LFXT1CLK: Low-frequency/high-frequency oscillator that can be used
either with low-frequency Hz watch crystals, or
standard crystals or resonators in the 450-kHz to 8-MHz range.
XT2CLK: Optional high-frequency oscillator that can be used with standard crystals, resonators, or external clock sources in the 450-kHz to 8-MHz range. In MSP430F47x devices the upper limit is 16 MHz.
DCOCLK: Internal digitally controlled oscillator (DCO) with RC-type characteristics, stabilized by the FLL.
Four clock signals are available from the FLL+ module:
ACLK: Auxiliary clock. The ACLK is the LFXT1CLK clock source. ACLK is software selectable for individual peripheral modules.
ACLK/n: Buffered output of the ACLK. The ACLK/n is ACLK divided by 1,2,4 or 8 and only used externally.
MCLK: Master clock. MCLK is software selectable as LFXT1CLK, XT2CLK (if available), or DCOCLK. MCLK can be divided by 1, 2, 4, or 8 within the FLL block. MCLK is used by the CPU and system.
SMCLK: Sub-main clock. SMCLK is software selectable as XT2CLK (if available), or DCOCLK. SMCLK is software selectable for individual peripheral modules.
CPE 323

56. FLL+ Clock Module Operation
After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times the ACLK frequency. When a 32,768-Hz crystal is used for ACLK, MCLK and SMCLK will stabilize to MHz.
Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure the MSP430 operating modes and enable or disable components of the FLL+ clock module.
The SCFQCTL, SCFI0, SCFI1, FLL_CTL0, and FLL_CTL1 registers configure the FLL+ clock module. The FLL+ can be configured or reconfigured by software at any time during program execution.
Example, MCLK = 64 × ACLK =
BIC #GIE,SR ; Disable interrupts
MOV.B #(64−1),&SCFQTL ; MCLK = 64 * ACLK, DCOPLUS=0
MOV.B #FN_2,&SCFIO ; Select DCO range
BIS #GIE,SR ; Enable interrupts
CPE 323

57. LFXT1 Oscillator
Low-frequency (LF) mode (XTS_FLL=0) with 32,768 Hz watch crystal connected to XIN and XOUT
High-frequency (HF) mode (XTS_FLL=1) with high-frequency crystals or resonators connected to XIN and XOUT (~450 KHz to 8 MHz)
XCPxPF bits configure the internally provided load capacitance for the LFXT1 crystal (1, 6, 8, or 10 pF)
OSCOFF bit can be set to disable LFXT1
CPE 323

58. XT2 Oscillator
XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode, except it does not have internal load capacitors (must be provided externally)
XT2OFF bit disables the XT2 oscillator if XT2CLK is not used for MCLK and SMCLK
CPE 323

59. DCO Integrated ring oscillator with RC-type characteristics
DCO frequency is stabilized by the FLL to a multiple of ACLK as defined by N (the lowest 7 bits of the SCFQCTL register)
DCOPLUS bit sets the fDCOCLK to fDCO or fDCO/D (divider). The FLLDx bits define the divider D to 1, 2, 4 or 8. By default DCOPLUS=0 and D=2, providing fDCOCLK= fDCO/2
DCOPLUS = 0: fDCOCLK = (N + 1) x fACLK
DCOPLUS = 1: fDCOCLK = D x (N + 1) x fACLK
CPE 323

60. DCO Frequency Range
CPE 323

61. Frequency Locked Loop
FLL continuously counts up or down a 10-bit frequency integrator.
The output of the frequency integrator that drives the DCO can be read in SCFI1 and SCFI0. The count is adjusted +1 or −1 with each ACLK crystal period.
Five of the integrator bits, SCFI1 bits 7-3, set the DCO frequency tap. Twenty-nine taps are implemented for the DCO (28, 29, 30, and 31 are equivalent), and each is approximately 10% higher than the previous. The modulator mixes two adjacent DCO frequencies to produce fractional taps.
SCFI1 bits 2-0 and SCFI0 bits 1-0 are used for the modulator.
The DCO starts at the lowest tap after a PUC or when SCFI0 and SCFI1 are cleared. Time must be allowed for the DCO to settle on the proper tap for normal operation. 32 ACLK cycles are required between taps requiring a worst case of 28 x 32 ACLK cycles for the DCO to settle
CPE 323

62. FLL+ Clock Module Registers
CPE 323