1. I/O PORTS : MSP430x5xx devices have up to 12 digital I/O ports :
P1 to P11 & PJ. Most ports have eight I/O pins, however some ports may contain less.
Each I/O pin is individually configurable for input (or) output direction, and each I/O line can be individually read or written to.
Ports P1 and P2 always have interrupt capability.
All ports have individually configurable pull-up (or) pull- down resistors, as well as, configurable drive strength.
Individual ports can be accessed as byte wide ports or can be combined into word wide ports i.e PA=P1&P2

2. Each port is assigned several 8-bit registers that control the function of the pins and provides information on their current status.
PxSEL (Port Selection) :
= 0 , digital I/O
= 1 , an alternate function
PxDIR (Port Direction) :
= 0 , input
= 1 , output
PxIN (Port Input) : Reads the voltage levels on input pins
PxOUT (Port Input) : Sends the value to be driven to each pin
PxREN ( Port Resistor Enable)
= 1 , Enables pull-up / pull-down resistors
= 0 , Disables pull-up / pull-down resistors

3. PxIE (Interrupt Enable) :
= 1 , Enables the interrupt
= 0 , Disables
PxIES ( Interrupt Edge Select) :
= 1 , falling-edge
= 0 , rising-edge
PxIFG (Interrupt Flag) : Set whenever the interrupt is detected on a particular pin

5. LED Interfacing
In the active high circuit, LED  ON if the pin outputs Logic HIGH
In the active low circuit, LED  ON if the pin outputs Logic LOW
A microcontroller is typically better at sinking current than sourcing it. Hence, the second method is employed for many applications.

7. Pull up/down Resistors Concepts
Pull-up and pull-down resistors are often used when interfacing a switch or some other inputs with a microcontroller.

8. Application of Pull up/down Resistors:
Interfacing of switches / other input devices with microcontrollers
In A/D converters to provide a controlled current flow into a resistive sensor. 
In I2C protocol bus

9. INTERRUPT
Interrupt is an event that causes the microcontroller to stop the normal program execution.
Why Interrupts?
Urgent tasks
Infrequent tasks
Waking the CPU from sleep
Calls to an operating system.

10. External & Internal interrupts
Interrupts are generated by external devices connected to the microcontroller.
Maskable & Non-maskable interrupts
if GIE = 0 , masking the interrupts
= 1 , un masking the interrupts
There are 3- non maskable interrupts:
Oscillator fault (OFIFG)
Access violation to flash memory (ACCVIFG)
An active edge on the external RST/NMI pin

11. Interrupt Service Routine :
The program to handle an interrupt is called an interrupt handler or Interrupt Service Routine (ISR).
The address of ISR is called as Interrupt vector.
The collection of all interrupt vectors is called interrupt vector table.
The MSP430 uses vectored interrupts. Each ISR has its own vector, which is stored at a predefined address in a vector table at the end of the program memory.

12. Processing of Interrupts:
The delay between an interrupt being requested and the start of the ISR is called the latency.

13. Processing of Interrupts:
The CPU completes the execution of current instruction.
The PC, which points to the next instruction, is pushed onto the stack.
The SR is pushed onto the stack.
The interrupt with the highest priority is selected if multiple interrupts are waiting for service.
The interrupt request flag is cleared automatically for vectors that have a single source.
The SR is cleared, which has two effects. First, further maskable interrupts are disabled because the GIE bit is cleared; non-maskable interrupts remain active. Second, it terminates any low-power mode.
The interrupt vector is loaded into the PC and the CPU starts to execute the interrupt service routine at that address.

15. Watchdog Timer
A watchdog timer is an electronic timer that is used to detect and recover from computer malfunctions.
The Watchdog Timer (WDT) module restarts the system on occurrence of a software problem (or) if a selected time interval expires.

16. Features of the watchdog timer
Four software-selectable time intervals
Watchdog mode
Interval mode
Access to WDT control register is password protected
Control of RST/NMI pin function
Selectable clock source
Can be stopped to conserve power
Clock fail-safe feature

17. Watchdog Timer Operation
The default period of the watchdog is the maximum value of 32,768 counts, which is therefore around 32 ms.
The WDT is clocked from either SMCLK (default) or ACLK, according to the WDTSSEL bit.
The operation of the watchdog is controlled by the 16-bit password-protected register WDTCTL.
If the watchdog function is not needed in an application, the module can be configured as an interval timer

20. Clock System in MSP430
Three clock signals are available from the basic clock module:
MCLK : Master clock is used by CPU and system
SMCLK : Subsystem Master clock is distributed to peripherals
ACLK : Auxiliary clock is also distributed to peripherals.

21. Very low-power, low-frequency oscillator, VLO:
The VLO is an internal RC oscillator that runs at around 12 KHz and can be used instead of LFXT1 in some devices.
Low- or high-frequency crystal oscillator, LFXT1:
used with a low-frequency watch crystal (32 KHz) but can also run with a high-frequency crystal (typically a few MHz)
High-frequency crystal oscillator, XT2:
used with standard crystals, resonators, or external clock sources in the 400-kHz to 16-MHz range.
Digitally controlled oscillator, DCO The DCO is an integrated digitally controlled oscillator and it is available in all devices. It is basically a highly controllable RC oscillator

23. Why low power?
Portable & mobile devices are getting popular, which have limited power sources, e.g., battery
Power generates heat
Power optimization becomes a new dimension in system design, besides performance and cost .
Energy conservation for our planet
Principles for Low-Power Applications
Provide clocks of different frequencies  frequency scaling
Lower supplied voltage  voltage scaling
Turn off clocks when no work to do  clock gating
Peripherals should be switched on only when needed.

24. Low-power modes of MSP430
The low-power modes 0 to 4 are configured with the CPUOFF, OSCOFF, SCG0, and SCG1 bits in the status register.
SCG1 SCG0 OSCOFF CPUOFF
Mode
CPU and Clocks Status
Active
CPU is active, all enabled clocks are active
LPM0
CPU & MCLK are disabled.
SMCLK & ACLK are active
LPM1
CPU & MCLK are disabled. ACLK is active.
DCO and DC generator are disabled if it is not used for SMCLK
LPM2
CPU, MCLK, SMCLK are disabled.
DC generator remains enabled. ACLK is active.
LPM3
CPU, MCLK, SMCLK, DCO & DC generators are disabled. ACLK is active.
LPM4
CPU and all clocks disabled

26. Introduction to the Timers of MSP430
Timers are essential in any embedded system. Timer applications are
Generate fixed-period events
Periodic wakeup
Count edges
Generate delays
Measures time intervals
Replacing delay loops with timer calls allows CPU to sleep, consuming less power

27. Five types of MSP430 timer modules are available
Five types of MSP430 timer modules are available. All devices contain two types of timer and some have five.
Basic timer1 : Present in the MSP430x4xx family only.
Timer_A : Present in all devices. It typically has 3 channels.
Timer_B : Included in larger devices of all families.
Watchdog timer : Included in all devices (newer ones have the enhanced WDT+).
Real-time clock : In which the basic timer has been extended to provide a real-time clock in the most recent MSP430x4xx devices.

28. TIMER_A Timer_A is a 16-bit timer/counter with 4- operating modes
Supports multiple capture/compare registers ( up to 7 CC registers)
Timer_A also has extensive interrupt capabilities.
Selectable and configurable clock source
PWM capability

29. Timer modes

30. Capture an input, which means recording the “time” (the value in TAR) at which the input changes in TACCRn.
Compare the current value of TAR with the value stored in TACCRx and update an output when they match
TAR- Timer A Register
TACCRx: Timer A Capture Compare Register

32. Capture Mode The capture mode is selected when CAP = 1.
Capture mode is used to record time events.
The CMx bits select the capture edge of the input signal as rising, falling, or both.
If a capture occurs:
The timer value is copied into the TACCRx register
The interrupt flag CCIFG is set

33. Compare Mode
The compare mode is selected when CAP = 0.
The compare mode is used to generate PWM output signals or interrupts at specific time intervals.
When TAR counts to the value in a TACCRx:
Interrupt flag CCIFG is set
EQUx affects the output according to the output mode
The input signal CCI is latched into SCCI
Each output unit has 8- operating modes, defined by the OUTMODx bits.

35. The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode.

42. PWM OUTPUT
Pulse-width modulation (PWM), or pulse-duration modulation (PDM), is a modulation technique used to encode a message into a pulsing signal.
The idea behind PWM is very simple: The output is switched on and off periodically so that the average voltage has the desired value.
The fraction of the time while the output is active is called the duty cycle D.
The duty cycle is always varied by keeping the period constant and changing the width of the pulses, hence the name of PWM.

45. Measurement in the Capture Mode
The Capture mode is used to take a time stamp of an event, and to note the time at which it occurred.
Measurement of duration and Time period
To measure the duration of the pulse, we should capture both rising and falling edges and subtract the captured times.
To measure the time period of the signal, we might capture only the rising edges (or falling if preferred) and the difference gives the period directly.

46. Measurement of frequency :
The signal is used as the timer clock (TACLK) and the edges of ACLK are captured whose frequency is known.
The difference between the captured value gives the number of cycles of the signal in one cycle of ACLK. This gives the frequency rather than the period.

47. Real-Time Clock (RTC)
The Real-Time Clock (RTC) is a timer module that provides a clock with calendar. It provides seconds, minutes, hours, day, month, and year.
Configurable for Real-Time Clock mode or 32-bit general purpose counter with the RTCMODEx bits.
The current time and date are held in a set of registers that contain the following bytes:
RTCSEC : Seconds
RTCMIN : Minute
RTCHOUR : Hour which runs from 0–23 (24-hour format).
RTCDOW : Day of week which runs from 0–6.
RTCDAY : Day of month (1-31)
RTCMON : Month (1-12)
RTCYEARL : Year, assuming BCD format.
RTCYEARH : Century, assuming BCD format.

49. Real-Time Clock Operation
Calendar Mode :
Calendar mode is selected when RTCMODEx = 11.
Switching from counter to calendar mode clears the seconds, minutes, hours, day-of-week, year counts and sets day-of-month and month counts to 1.
When RTCBCD = 1, BCD format is selected for the calendar registers.
Counter Mode :
Counter mode is selected when RTCMODEx < 11.
In this mode, a 32-bit counter is provided that is directly accessible by software.
Switching from calendar mode to counter mode resets the count value.

50. Real-Time Clock control register

51. COMPARATOR
An analog comparator compares the voltages on its two input terminals, V+ and V−.
The comparator output CAOUT is high if V+ > V− and low if V+ < V−.
The comparator can be switched ON or OFF using control bit CAON.
It provides a basic bridge between analog & digital domains and acts as a 1-bit ADC

54. The ADC10 : Successive Approximation ADC
The ADC10 module supports fast, 10-bit analog-to-digital conversions.
The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC).
The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention.

57. Interfacing diagram

59. DMA Controller DMA controller features:
Three independent transfer channels.
Two DMA channel priorities with the ROUNDROBIN bit.(default: DMA0−DMA1−DMA2).
DMA Transfer cycle time: Requires only two MCLK clock cycles per transfer.
Byte or word and mixed byte/word transfer capability.
Block sizes up to bytes or words.
Configurable selection of transfer trigger.
Selectable edge or level-triggered transfer (DMALEVEL bit).
Four addressing modes.

61. DMA REQUEST PRIORITIES
Default priority
DMA0 has highest priority followed by DMA1& DMA2.
Round Robin priority

63. FRAM vs FLASH
Ferroelectric Random Access Memory (FRAM) is an ultra-low power non-volatile memory technology with write speeds similar to static RAM (SRAM).
FRAM
FLASH
1.FRAM is non-volatile; that is, it retains its contents on loss of power.
1.FLASH is non-volatile memory that can be electrically erased and reprogrammed.
2. FRAM is a true random-access memory i.e. The memory is not segmented
2. Flash devices have segmented
Memory.
3.Typical write speeds can exceed 2 MBps with FRAM
3. Typical write speeds can be 14 KBps with Flash devices.
4. FRAM write accesses are extremely low power.
4. Flash write accesses are not extremely low power
5. FRAM writes can be performed across the full voltage range of the device
5.Flash writes cannot be performed across the full voltage range of the device