R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 1 Dr. Esam Al_Qaralleh.

Slides:



Advertisements
Similar presentations
Instruction Clock Cycles Generally, 1 cycle per memory access: – 1 cycle to fetch instruction word – +1 cycle if or #Imm – +2 cycles.
Advertisements

Fetch-Execute cycle. Memory Read operation Read from memory.
The Fetch – Execute Cycle
Central Processing Unit
Slide 4-1 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Computer Organization.
Arithmetic Logic Unit (ALU)
CS1104: Computer Organisation School of Computing National University of Singapore.
Topics covered: CPU Architecture CSE 243: Introduction to Computer Architecture and Hardware/Software Interface.
1 HW #6 Write an assembly program to calculate the sum of the ten scores stored in memory as shown on the right. You can use any instruction used in the.
CPU Design. CS252/Culler Lec 1.2 1/22/02 Levels of Representation (61C Review) High Level Language Program Assembly Language Program Machine Language.
The CPU. Parts of the CPU Control Unit Arithmetic & Logic Unit Registers.
Execution of an instruction
Topics covered: CPU Architecture CSE 243: Introduction to Computer Architecture and Hardware/Software Interface.
Chapters 5 - The LC-3 LC-3 Computer Architecture Memory Map
Chapter 7. Basic Processing Unit
Dale & Lewis Chapter 5 Computing components. Let’s design a computer Generic CPU with registers −Program counter (PC) – 5 bits (size of addresses) −Instruction.
Lecture 13 - Introduction to the Central Processing Unit (CPU)
CPU Fetch/Execute Cycle
Computer Science 210 Computer Organization The Instruction Execution Cycle.
The von Neumann Model – Chapter 4 COMP 2620 Dr. James Money COMP
Computer Science 210 Computer Organization The von Neumann Architecture.
Multiple-bus organization
EXECUTION OF COMPLETE INSTRUCTION
Computer Architecture Lecture 09 Fasih ur Rehman.
The von Neumann Model – Chapter 4
REGISTER TRANSFER & MICROOPERATIONS By Sohaib. Digital System Overview  Each module is built from digital components  Registers  Decoders  Arithmetic.
Model Computer CPU Arithmetic Logic Unit Control Unit Memory Unit
The structure COMPUTER ARCHITECTURE – The elementary educational computer.
In1210/01-PDS 1 TU-Delft The Processing Unit. in1210/01-PDS 2 TU-Delft Problem f y ALU y Decoder a instruction Reg ?
Fetch-execute cycle.
1/8/ Data Path Design & Control Copyright Joanne DeGroat, ECE, OSU1 Processor Data Paths - ALU and Registers Incorporating the ALU into a.
Computer Science 101 Computer Systems Organization Machine Language Examples Entire machine.
Computer Systems - Registers. Starter… Discuss in pairs the definition of the following Control Unit Arithmetic and Logic Unit Registers Internal clock.
Computer Architecture Lecture 03 Fasih ur Rehman.
COMPILERS CLASS 22/7,23/7. Introduction Compiler: A Compiler is a program that can read a program in one language (Source) and translate it into an equivalent.
Computer Systems Organization
The von Neumann Model – Chapter 4 COMP 2620 Dr. James Money COMP
© BYU LC3-DC Page 1 ECEn 224 LC3-DC Designing The LC-3 Control IR PC enaMARMenaPC enaALU enaMDR ALU AB.
Chapter 3 Basic Processing Unit.
COEN 311 Computer Organization & Software Chapter 1 Introduction and Terminology (Prof. Sofiène Tahar) Concordia University Electrical & Computer Engineering.
Please see “portrait orientation” PowerPoint file for Chapter 7 Figure 7.1. Single-bus organization of the datapath inside a processor.
RegDst 1: RegFile destination No. for the WR Reg. comes from rd field. 0: RegFile destination No. for the WR Reg. comes from rt field.
REGISTER TRANSFER & MICROOPERATIONS By Sohaib. Digital System Overview  Each module is built from digital components  Registers  Decoders  Arithmetic.
Chapter 20 Computer Operations Computer Studies Today Chapter 20.
Lec 4-2 Five operations of the machine cycle Fetch- fetch the next program instruction from memory. (PC+1); instruction to IR Decode- decode the instruction.
Fundamental of Computer Architecture By Panyayot Chaikan ac.th Ocbober 25, 2004.
Control Unit Design.
Computer Science 210 Computer Organization
Computer Organization
Computer Science 210 Computer Organization
UNIT 4 Control Unit. UNIT 4 Control Unit Single CPU Bus CPU Bus MUX Temp PC R0 R(n-1) Instruction Decoder IR MAR MDR Z Y ALU Carry In Address Lines.
Computer Science 210 Computer Organization
Basic Processing Unit Unit- 7 Engineered for Tomorrow CSE, MVJCE.
Computer Science 210 Computer Organization
Functional Units.
COMS 161 Introduction to Computing
Instruction and Control II
Computer Structure S.Abinash 11/29/ _02.
Topic 6 LC-3.
المدخل إلى تكنولوجيا التعليم في ضوء الاتجاهات الحديثة
Some Fundamental Concepts
Chapter 7. Basic Processing Unit
The Little Man Computer
Chapter 7. Basic Processing Unit
Fundamental Concepts Processor fetches one instruction at a time and perform the operation specified. Instructions are fetched from successive memory locations.
THE FETCH-EXECUTE CYCLE.
Basic Processing Unit UNIT-5.
パイプライン化してないPICO Controller ALU sbus1 sbus2 pc ir register file dbus
THE FETCH-EXECUTE CYCLE.
Computer Architecture
Presentation transcript:

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 1 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y IR Control/Decode Unite Pc out, MAR in, Read, Select4, Add, Z in Z Z Constant 4 R2R2 R2R2 2 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y IR Control/Decode Unite Pc out, MAR in, Read, Select4, Add, Z in Z Z Constant 4 MAR R2R2 R2R2 3 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y IR Control/Decode Unite Pc out, MAR in, Read, Select4, Add, Z in Z Z Constant 4 MAR Read R2R2 R2R2 4 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y IR Control/Decode Unite Pc out, MAR in, Read, Select4, Add, Z in Z Z Constant 4 MAR Read Select4 R2R2 R2R2 5 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y IR Control/Decode Unite Pc out, MAR in, Read, Select4, Add, Z in Z Z Constant 4 MAR Read Select4 ADD PC+4 R2R2 R2R2 6 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y IR Control/Decode Unite Pc out, MAR in, Read, Select4, Add, Z in Z Z Constant 4 MAR Read Select4 ADD PC+4 Z Z R2R2 R2R2 7 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 Z out, Pc in, Y in, WMFC R2R2 R2R2 R2R2 R2R2 8 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 Z out, Pc in, Y in, WMFC PC R2R2 R2R2 9 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 Z out, Pc in, Y in, WMFC PC Y Y R2R2 R2R2 10 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 Z out, Pc in, Y in, WMFC PC Y Y WMFC Waiting for the Data to come from the memory. When the data or Instruction is available, it will be Latched into MDR R2R2 R2R2 11 Dr. Esam Al_Qaralleh

R1R1 R1R1 R1R1 R1R1 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 MDR out, IR in PC Y Y R2R2 R2R2 12 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 MDR out, IR in PC Y Y IR ADD R1, R2 13 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 R1 out, Y in, SELECTY PC Y Y IR ADD R1, R2 14 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 R1 out, Y in, SELECTY PC Y Y IR ADD R1, R2 Y Y 15 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 R1 out, Y in, SELECTY PC Y Y IR ADD R1, R2 Y Y SelectY 16 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 R2 out, ADD, Z in PC Y Y IR ADD R1, R2 Y Y SelectY 17 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 R2 out, ADD, Z in PC Y Y IR ADD R1, R2 Y Y SelectY ADD 18 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 R2 out, ADD, Z in PC Y Y IR ADD R1, R2 Y Y SelectY ADD Z Z 19 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 Zout, R1 in, END PC Y Y IR ADD R1, R2 Y Y SelectY ADD Z Z 20 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 Zout, R1 in, END PC Y Y IR ADD R1, R2 Y Y SelectY ADD Z Z R1R1 R1R1 21 Dr. Esam Al_Qaralleh

R1R1 R1R1 R2R2 R2R2 PC MDR MAR Y Y Z Z IR Control/Decode Unite Constant 4 Zout, R1 in, END PC Y Y IR ADD R1, R2 Y Y SelectY ADD Z Z R1R1 R1R1 22 Dr. Esam Al_Qaralleh