1. パイプライン化してないPICO Controller ALU sbus1 sbus2 ｐｃ ir register file dbus
mar
mdr
Address bus
Data bus
Memory

2. PICOのパイプライン構造 IF RF EX WB 2 ＋ ALU Data Memory Instruction Memory RFPC
rega
regc ＋
ALU
IFPC
regb c b
Imm.
wadr
IFIR
RFIR
Data
Memory
Instruction
Memory

3. Data Memory Instruction Memory
LDLI r1,#1
RFPC IF RF EX WB a 2
rega
regc ＋
ALU
IFPC
regb c b
Imm.
wadr
IFIR
RFIR
Data
Memory
Instruction
Memory

4. Data Memory Instruction Memory
LDLI r2,#2
LDLI r1,#1
RFPC IF RF EX WB a 2
rega
regc ＋
ALU
IFPC
regb c b
Imm.
wadr
IFIR
RFIR
Data
Memory
Instruction
Memory

5. Data Memory Instruction Memory
LDLI r3,#3
LDLI r2,#2
LDLI r1,#1
RFPC IF RF EX WB a 2
rega
regc ＋ 1
ALU
IFPC
regb c b
Imm.
wadr
IFIR
RFIR
Data
Memory
Instruction
Memory

6. Data Memory Instruction Memory
ADD r1,#2
LDLI r3,#3
LDLI r2,#2
LDLI r1,#1
RFPC IF RF EX WB a 2
rega
regc 1 ＋ 2
ALU
IFPC
regb c b
Imm.
wadr
IFIR
RFIR
Data
Memory
Instruction
Memory

7. Data Memory Instruction Memory
ADD r2,r2
ADD r1,#2
LDLI r3,#3
LDLI r2,#2
RFPC IF RF EX WB a 2
rega
regc 2 ＋ 3
ALU
IFPC
regb c b
Imm.
wadr
IFIR
RFIR
Data
Memory
Instruction
Memory

8. Data Memory Instruction Memory
ADD r2,r2
ADD r1,#2
LDLI r3,#3
RFPC IF RF EX WB a 2
rega
regc 3 ＋ 3
ALU
IFPC
regb c b
Imm.
wadr
IFIR
RFIR
Data
Memory
Instruction
Memory

9. Data Memory Instruction Memory
ADD r2,r2
ADD r1,#2
RFPC IF RF EX WB a 2
rega
regc 3 ＋ 4
ALU
IFPC
regb c b
Imm.
wadr
IFIR
RFIR
Data
Memory
Instruction
Memory

10. Data Memory Instruction Memory
ADD r2,r2
RFPC IF RF EX WB a 2
rega
regc 4 ＋
ALU
IFPC
regb c b
Imm.
wadr
IFIR
RFIR
Data
Memory
Instruction
Memory