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Fundamental of Computer Architecture By Panyayot Chaikan panyayot@coe.psu. ac.th 240-208 Ocbober 25, 2004
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Chapter 3 - The Processing Unit 2 240-208 Fundamental of Computer Architecture Chapter 3 โพรเซสเซอร์และการ ทำงาน The Processing Unit
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Chapter 3 - The Processing Unit 3 240-208 Fundamental of Computer Architecture เนื้อหา นิยาม และคำศัพท์ที่ควรรู้เกี่ยวกับไมโคร โพรเซสเซอร์และ ไมโครคอมพิวเตอร์ ประวัติความเป็นมาของไมโครโพรเซสเซอร์ ข้อดีข้อเสียของไมโครโพรเซสเซอร์ ข้อพิจารณาในการเลือกใช้ไมโครโพรเซสเซอร์
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Chapter 3 - The Processing Unit 4 240-208 Fundamental of Computer Architecture Computer BUS A group of wires that connects several devices Three types of Bus Address bus Data bus Control bus
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Chapter 3 - The Processing Unit 5 240-208 Fundamental of Computer Architecture Address bus Used to specify memory location that the cpu want to access(read/write) n-bit address bus provides 2 n addresses For Example MCS-51 16-bit address bus-> 2 16 = 16 Kbyte of memory 8086 20-bit address bus -> 2 20 = 1 Mbyte of memory Pentium 32-bit address bus -> 2 32 = 4 Gbyte of memory
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Chapter 3 - The Processing Unit 6 240-208 Fundamental of Computer Architecture Databus Used to sent data between CPU and peripheral(memory, i/o) The more bit of data bus, the more speed achieved For Example MCS-51 8-bit data bus 8086 16-bit data bus Pentium 64-bit data bus
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Chapter 3 - The Processing Unit 7 240-208 Fundamental of Computer Architecture BUS
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Chapter 3 - The Processing Unit 8 240-208 Fundamental of Computer Architecture CPU : Basic operations Fetch : Read the instructions and data from memory Execute : perform the desired operation and write the result into the memory or registers
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Chapter 3 - The Processing Unit 9 240-208 Fundamental of Computer Architecture FETCH
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Chapter 3 - The Processing Unit 10 240-208 Fundamental of Computer Architecture
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Chapter 3 - The Processing Unit 11 240-208 Fundamental of Computer Architecture Terminology IR : Instruction Register MAR : Memory Address Register
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Chapter 3 - The Processing Unit 12 240-208 Fundamental of Computer Architecture Instructions of CPU There are 4 types of instructions 1. Data transfer between memory and CPU registers 2. Arithmetic and Logic Operations on data 3. Program Sequencing and Control 4. I/O transfer
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Chapter 3 - The Processing Unit 13 240-208 Fundamental of Computer Architecture Basic instruction types : three address instruction LOAD R0,[10000] LOAD R1,[10001] ADD R2, R0, R1 LOAD R0,[10002] ADD R1, R0,R2 STORE [10003],R1 D = A+B+C Note ADD R2,R0,R1 means R2 = R0+R1
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic instruction types : three address instruction LOAD R0,[10000] LOAD R1,[10001] ADD R2, R0, R1 LOAD R0,[10002] ADD R1, R0,R2 STORE [10003],R1 D = A+B+C Note ADD R2,R0,R1 means R2 = R0+R1](http://images.slideplayer.com/37/10703440/slides/slide_13.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic instruction types : three address instruction LOAD R0,[10000] LOAD R1,[10001] ADD R2, R0, R1 LOAD R0,[10002] ADD R1, R0,R2 STORE [10003],R1 D = A+B+C Note ADD R2,R0,R1 means R2 = R0+R1")
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Chapter 3 - The Processing Unit 14 240-208 Fundamental of Computer Architecture Basic instruction types : two address instruction LOAD R0,[10000] LOAD R1,[10001] ADD R0,R1 LOAD R2,[10002] ADD R0,R2 STORE [10003],R0 D = A+B+C Note ADD R0,R1 means R0 = R0+R1
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic instruction types : two address instruction LOAD R0,[10000] LOAD R1,[10001] ADD R0,R1 LOAD R2,[10002] ADD R0,R2 STORE [10003],R0 D = A+B+C Note ADD R0,R1 means R0 = R0+R1](http://images.slideplayer.com/37/10703440/slides/slide_14.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic instruction types : two address instruction LOAD R0,[10000] LOAD R1,[10001] ADD R0,R1 LOAD R2,[10002] ADD R0,R2 STORE [10003],R0 D = A+B+C Note ADD R0,R1 means R0 = R0+R1")
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Chapter 3 - The Processing Unit 15 240-208 Fundamental of Computer Architecture Basic instruction types : one address instruction LOAD [10000] ADD [10001] ADD [10002] STORE [10003] D = A+B+C Note ADD [10001] means Acc = Acc + [10001]
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic instruction types : one address instruction LOAD [10000] ADD [10001] ADD [10002] STORE [10003] D = A+B+C Note ADD [10001] means Acc = Acc + [10001]](http://images.slideplayer.com/37/10703440/slides/slide_15.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic instruction types : one address instruction LOAD [10000] ADD [10001] ADD [10002] STORE [10003] D = A+B+C Note ADD [10001] means Acc = Acc + [10001]")
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Chapter 3 - The Processing Unit 16 240-208 Fundamental of Computer Architecture CPU registers General purpose registers R0,R1…Rn A,B, C,…. Special purpose register PC SP Accumulator Flag or Condition code
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Chapter 3 - The Processing Unit 17 240-208 Fundamental of Computer Architecture PC :Program Counter register Used to keep the next address of memory that CPU want to access PC and address-bus have the same size
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Chapter 3 - The Processing Unit 18 240-208 Fundamental of Computer Architecture PC :Program Counter (continued)
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Chapter 3 - The Processing Unit 19 240-208 Fundamental of Computer Architecture PC :Program Counter (continued)
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Chapter 3 - The Processing Unit 20 240-208 Fundamental of Computer Architecture PC :Program Counter (continued)
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Chapter 3 - The Processing Unit 21 240-208 Fundamental of Computer Architecture PC :Program Counter (continued)
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Chapter 3 - The Processing Unit 22 240-208 Fundamental of Computer Architecture PC :Program Counter (continued)
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Chapter 3 - The Processing Unit 23 240-208 Fundamental of Computer Architecture PC :Program Counter (continued)
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Chapter 3 - The Processing Unit 24 240-208 Fundamental of Computer Architecture Branching LOC35000:LOAD R0,#0 LOAD R1,#14999 LOAD R3,#10000 LOC35003:LOAD R2,[R3] ADD R0, R2 INC R3 DEC R1 Branch_NZ LOC35003 STORE [R3],R0 [25000] = [10000]+[10002]+[10003]+….+[ 24999]
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Branching LOC35000:LOAD R0,#0 LOAD R1,#14999 LOAD R3,#10000 LOC35003:LOAD R2,[R3] ADD R0, R2 INC R3 DEC R1 Branch_NZ LOC35003 STORE [R3],R0 [25000] = [10000]+[10002]+[10003]+….+[ 24999]](http://images.slideplayer.com/37/10703440/slides/slide_24.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Branching LOC35000:LOAD R0,#0 LOAD R1,#14999 LOAD R3,#10000 LOC35003:LOAD R2,[R3] ADD R0, R2 INC R3 DEC R1 Branch_NZ LOC35003 STORE [R3],R0 [25000] = [10000]+[10002]+[10003]+….+[ 24999]")
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Chapter 3 - The Processing Unit 25 240-208 Fundamental of Computer Architecture Flag or Condition code Register keep the status after perform arithmetic and logic operation Example: Flags of CPU z80
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Chapter 3 - The Processing Unit 26 240-208 Fundamental of Computer Architecture Addressing modes of CPU Immediate#value load R0,#00001 RegisterRiload R0,R1 Direct(absolute)[mem_loc] load R0,[100000] Register indirect[Ri]load R0,[R1] RelativeX[PC] Index
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Addressing modes of CPU Immediate#value load R0,#00001 RegisterRiload R0,R1 Direct(absolute)[mem_loc] load R0,[100000] Register indirect[Ri]load R0,[R1] RelativeX[PC] Index](http://images.slideplayer.com/37/10703440/slides/slide_26.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Addressing modes of CPU Immediate#value load R0,#00001 RegisterRiload R0,R1 Direct(absolute)[mem_loc] load R0,[100000] Register indirect[Ri]load R0,[R1] RelativeX[PC] Index")
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Chapter 3 - The Processing Unit 27 240-208 Fundamental of Computer Architecture Immediate addressing load R1,#00001
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Chapter 3 - The Processing Unit 28 240-208 Fundamental of Computer Architecture Direct addressing LOAD R1,[1200H]
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Direct addressing LOAD R1,[1200H]](http://images.slideplayer.com/37/10703440/slides/slide_28.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Direct addressing LOAD R1,[1200H]")
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Chapter 3 - The Processing Unit 29 240-208 Fundamental of Computer Architecture Register indirect load R0,[R1]
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Register indirect load R0,[R1]](http://images.slideplayer.com/37/10703440/slides/slide_29.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Register indirect load R0,[R1]")
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Chapter 3 - The Processing Unit 30 240-208 Fundamental of Computer Architecture Index addressing Use index register Effective address = X + [Ri] When X = offset (or displacement) Ri = index register or Base register
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Index addressing Use index register Effective address = X + [Ri] When X = offset (or displacement) Ri = index register or Base register](http://images.slideplayer.com/37/10703440/slides/slide_30.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Index addressing Use index register Effective address = X + [Ri] When X = offset (or displacement) Ri = index register or Base register")
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Chapter 3 - The Processing Unit 31 240-208 Fundamental of Computer Architecture Index addressing Offset is given as a constant
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Chapter 3 - The Processing Unit 32 240-208 Fundamental of Computer Architecture Index addressing Offset is in the index register
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Chapter 3 - The Processing Unit 33 240-208 Fundamental of Computer Architecture Example1 : Transfering bytes of data Copy values in memory location 1000h-1400h to location 2000h-2400h (1024 byte)
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Chapter 3 - The Processing Unit 34 240-208 Fundamental of Computer Architecture Example1 : Transfering bytes of data STRT:LD R0,#1000H LD R1,#2000H LD R3,#1024 LOC_A:LD R4, [R0] STORE [R1], R4 INC R0 INC R1 DEC R3 BRANCH>0 LOC_A CALL PRINTF
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example1 : Transfering bytes of data STRT:LD R0,#1000H LD R1,#2000H LD R3,#1024 LOC_A:LD R4, [R0] STORE [R1], R4 INC R0 INC R1 DEC R3 BRANCH>0 LOC_A CALL PRINTF](http://images.slideplayer.com/37/10703440/slides/slide_34.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example1 : Transfering bytes of data STRT:LD R0,#1000H LD R1,#2000H LD R3,#1024 LOC_A:LD R4, [R0] STORE [R1], R4 INC R0 INC R1 DEC R3 BRANCH>0 LOC_A CALL PRINTF")
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Chapter 3 - The Processing Unit 35 240-208 Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition Multiply 8-bit unsigned number C = A * B
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Chapter 3 - The Processing Unit 36 240-208 Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition
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Chapter 3 - The Processing Unit 37 240-208 Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition STRT:LOAD R1,#0 LOAD R3, [mem_loc_A] LOAD R2, [mem_loc_B] LOOP:ADD R1,R3 DEC R2 BRANCH>0 LOOP STORE [mem_loc_C],R1 CALL PRINTF
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition STRT:LOAD R1,#0 LOAD R3, [mem_loc_A] LOAD R2, [mem_loc_B] LOOP:ADD R1,R3 DEC R2 BRANCH>0 LOOP STORE [mem_loc_C],R1 CALL PRINTF](http://images.slideplayer.com/37/10703440/slides/slide_37.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition STRT:LOAD R1,#0 LOAD R3, [mem_loc_A] LOAD R2, [mem_loc_B] LOOP:ADD R1,R3 DEC R2 BRANCH>0 LOOP STORE [mem_loc_C],R1 CALL PRINTF")
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Chapter 3 - The Processing Unit 38 240-208 Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition Problem of the program in page 37 If B = 0 then the result is A, not 0 How to remedy the problem
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Chapter 3 - The Processing Unit 39 240-208 Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition STRT:LOAD R1,#0 LOAD R3, [mem_loc_A] LOAD R2, [mem_loc_B] Compare R2,#0 Branch_Z STR LOOP:ADD R1,R3 DEC R2 Branch>0 LOOP STR:STORE [mem_loc_C],R1
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition STRT:LOAD R1,#0 LOAD R3, [mem_loc_A] LOAD R2, [mem_loc_B] Compare R2,#0 Branch_Z STR LOOP:ADD R1,R3 DEC R2 Branch>0 LOOP STR:STORE [mem_loc_C],R1](http://images.slideplayer.com/37/10703440/slides/slide_39.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition STRT:LOAD R1,#0 LOAD R3, [mem_loc_A] LOAD R2, [mem_loc_B] Compare R2,#0 Branch_Z STR LOOP:ADD R1,R3 DEC R2 Branch>0 LOOP STR:STORE [mem_loc_C],R1")
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Chapter 3 - The Processing Unit 40 240-208 Fundamental of Computer Architecture Example3: if-then-else if (mem_loc_a == 5) mem_loc_b++; else mem_loc_b = mem_loc_a + mem_loc_b;
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Chapter 3 - The Processing Unit 41 240-208 Fundamental of Computer Architecture Example3: if-then-else Load R1,[mem_loc_a] Load R2,[mem_loc_b] Compare r1,#5 Branch_NZ b_p_a incr2 branchstre b_p_a:Add r2,r1 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example3: if-then-else Load R1,[mem_loc_a] Load R2,[mem_loc_b] Compare r1,#5 Branch_NZ b_p_a incr2 branchstre b_p_a:Add r2,r1 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2](http://images.slideplayer.com/37/10703440/slides/slide_41.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example3: if-then-else Load R1,[mem_loc_a] Load R2,[mem_loc_b] Compare r1,#5 Branch_NZ b_p_a incr2 branchstre b_p_a:Add r2,r1 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2")
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Chapter 3 - The Processing Unit 42 240-208 Fundamental of Computer Architecture Example4: checking greater-than if (mem_loc_a > 5) mem_loc_b++; else mem_loc_b = mem_loc_a + mem_loc_b;
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Chapter 3 - The Processing Unit 43 240-208 Fundamental of Computer Architecture Example4: checking greater-than Load R1,[mem_loc_a] Load R2,[mem_loc_b] comparer1,#5 branch_z equ_g_5;equal 5 branch_Mequ_g_5;M= minus incr2 branchstre equ_g_5:Add r2,r1 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example4: checking greater-than Load R1,[mem_loc_a] Load R2,[mem_loc_b] comparer1,#5 branch_z equ_g_5;equal 5 branch_Mequ_g_5;M= minus incr2 branchstre equ_g_5:Add r2,r1 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2](http://images.slideplayer.com/37/10703440/slides/slide_43.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example4: checking greater-than Load R1,[mem_loc_a] Load R2,[mem_loc_b] comparer1,#5 branch_z equ_g_5;equal 5 branch_Mequ_g_5;M= minus incr2 branchstre equ_g_5:Add r2,r1 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2")
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Chapter 3 - The Processing Unit 44 240-208 Fundamental of Computer Architecture Example4: checking greater-than Load R1,[mem_loc_a] Load R2,[mem_loc_b] sub r1,#5 branch>0 gt_5 Add r2,r1 branchstre gt_5:incr2 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example4: checking greater-than Load R1,[mem_loc_a] Load R2,[mem_loc_b] sub r1,#5 branch>0 gt_5 Add r2,r1 branchstre gt_5:incr2 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2](http://images.slideplayer.com/37/10703440/slides/slide_44.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example4: checking greater-than Load R1,[mem_loc_a] Load R2,[mem_loc_b] sub r1,#5 branch>0 gt_5 Add r2,r1 branchstre gt_5:incr2 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2")
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Chapter 3 - The Processing Unit 45 240-208 Fundamental of Computer Architecture Basic processing unit the structure of simple CPU How the internal parts of CPU work How to design the simple processor Datapath Control Unit
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Chapter 3 - The Processing Unit 46 240-208 Fundamental of Computer Architecture Inside simple CPU with Single-bus Datapath
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Chapter 3 - The Processing Unit 47 240-208 Fundamental of Computer Architecture Single-bus CPU architecture 32-bit CPU 16 instructions Fixed length instruction format 32 general purpose registers(R0-R31)
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Chapter 3 - The Processing Unit 48 240-208 Fundamental of Computer Architecture CPU instructions COMPARE Ry,#data Branch rel Branch NZ,rel Branch Z,rel Branch M,rel INC Ry INVERT Ry SHL Ry LD Rx,Ry LD Ry,#data LD Ry,[Rx] STORE [Ry],Rx ADD Rx,Ry SUB Rx,Ry OR Rx,Ry AND Rx,Ry
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture CPU instructions COMPARE Ry,#data Branch rel Branch NZ,rel Branch Z,rel Branch M,rel INC Ry INVERT Ry SHL Ry LD Rx,Ry LD Ry,#data LD Ry,[Rx] STORE [Ry],Rx ADD Rx,Ry SUB Rx,Ry OR Rx,Ry AND Rx,Ry](http://images.slideplayer.com/37/10703440/slides/slide_48.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture CPU instructions COMPARE Ry,#data Branch rel Branch NZ,rel Branch Z,rel Branch M,rel INC Ry INVERT Ry SHL Ry LD Rx,Ry LD Ry,#data LD Ry,[Rx] STORE [Ry],Rx ADD Rx,Ry SUB Rx,Ry OR Rx,Ry AND Rx,Ry")
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Chapter 3 - The Processing Unit 49 240-208 Fundamental of Computer Architecture LD Ry,Rx Copy value in Rx register into Ry register Rx remains its own value For instance: LD R2,R1
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Chapter 3 - The Processing Unit 50 240-208 Fundamental of Computer Architecture LD Ry,#data Load Ry with constant value For instance: LD R3,#25H
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Chapter 3 - The Processing Unit 51 240-208 Fundamental of Computer Architecture LD Ry,[Rx] Read data from specified memoy location into Ry For instance: LD R2,[R1]
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture LD Ry,[Rx] Read data from specified memoy location into Ry For instance: LD R2,[R1]](http://images.slideplayer.com/37/10703440/slides/slide_51.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture LD Ry,[Rx] Read data from specified memoy location into Ry For instance: LD R2,[R1]")
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Chapter 3 - The Processing Unit 52 240-208 Fundamental of Computer Architecture LD Ry,[Rx] Read data from specified memoy location into Ry For instance: LD R2,[R1]
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture LD Ry,[Rx] Read data from specified memoy location into Ry For instance: LD R2,[R1]](http://images.slideplayer.com/37/10703440/slides/slide_52.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture LD Ry,[Rx] Read data from specified memoy location into Ry For instance: LD R2,[R1]")
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Chapter 3 - The Processing Unit 53 240-208 Fundamental of Computer Architecture LD Ry,[Rx] Read data from specified memoy location into Ry For instance: LD R2,[R1]
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture LD Ry,[Rx] Read data from specified memoy location into Ry For instance: LD R2,[R1]](http://images.slideplayer.com/37/10703440/slides/slide_53.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture LD Ry,[Rx] Read data from specified memoy location into Ry For instance: LD R2,[R1]")
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Chapter 3 - The Processing Unit 54 240-208 Fundamental of Computer Architecture STORE [Ry],Rx Copy data in Rx register into memory location pointed by Ry register For instance: STORE [R6], R1
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture STORE [Ry],Rx Copy data in Rx register into memory location pointed by Ry register For instance: STORE [R6], R1](http://images.slideplayer.com/37/10703440/slides/slide_54.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture STORE [Ry],Rx Copy data in Rx register into memory location pointed by Ry register For instance: STORE [R6], R1")
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Chapter 3 - The Processing Unit 55 240-208 Fundamental of Computer Architecture STORE [Ry],Rx Copy data in Rx register into memory location pointed by Ry register For instance: STORE [R6], R1
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture STORE [Ry],Rx Copy data in Rx register into memory location pointed by Ry register For instance: STORE [R6], R1](http://images.slideplayer.com/37/10703440/slides/slide_55.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture STORE [Ry],Rx Copy data in Rx register into memory location pointed by Ry register For instance: STORE [R6], R1")
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Chapter 3 - The Processing Unit 56 240-208 Fundamental of Computer Architecture STORE [Ry],Rx Copy data in Rx register into memory location pointed by Ry register For instance: STORE [R6], R1
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture STORE [Ry],Rx Copy data in Rx register into memory location pointed by Ry register For instance: STORE [R6], R1](http://images.slideplayer.com/37/10703440/slides/slide_56.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture STORE [Ry],Rx Copy data in Rx register into memory location pointed by Ry register For instance: STORE [R6], R1")
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Chapter 3 - The Processing Unit 57 240-208 Fundamental of Computer Architecture ADD Ry,Rx Ry = Ry + Rx For instance: ADD R1,R3
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Chapter 3 - The Processing Unit 58 240-208 Fundamental of Computer Architecture SUB Ry,Rx Ry = Ry - Rx For instance: SUB R1,R3
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Chapter 3 - The Processing Unit 59 240-208 Fundamental of Computer Architecture AND Ry,Rx Ry = Ry 1 For instance: AND R1,R2
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Chapter 3 - The Processing Unit 60 240-208 Fundamental of Computer Architecture OR Ry,Rx Ry = Ry 1 For instance: OR R1,R2
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Chapter 3 - The Processing Unit 61 240-208 Fundamental of Computer Architecture COMPARE Ry,#data ALU performs Ry - data Status of operation displayed in Flag For instance: COMPARE R7,#50
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Chapter 3 - The Processing Unit 62 240-208 Fundamental of Computer Architecture Branch rel Branch to relative address location unconditional branch Effective address = PC+4+rel
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Chapter 3 - The Processing Unit 63 240-208 Fundamental of Computer Architecture Branch NZ,rel Conditional branch Branch to relative address location if Zero flag is not set(Non Zero) if Z = 0 then Effective address = PC+4+rel else Effective address = current PC
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Chapter 3 - The Processing Unit 64 240-208 Fundamental of Computer Architecture Branch Z,rel Conditional branch Branch to relative address location if Zero flag is set if Z = 1 then Effective address = PC+4+rel else Effective address = current PC
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Chapter 3 - The Processing Unit 65 240-208 Fundamental of Computer Architecture Branch M,rel Conditional branch Branch to relative address location if Sign flag is set (Minus) if Negative_Flag = 1 then Effective address = PC+4+rel else Effective address = current PC
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Chapter 3 - The Processing Unit 66 240-208 Fundamental of Computer Architecture INC Ry Ry = Ry + 1 For instance: INC R5
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Chapter 3 - The Processing Unit 67 240-208 Fundamental of Computer Architecture INVERT Ry Ry = not Ry For instance: INVERT R4
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Chapter 3 - The Processing Unit 68 240-208 Fundamental of Computer Architecture SHL Ry Shift Left Ry Ry n <= Ry n-1, n = 31 downto 1 Ry 0 <= ‘0’ For instance: SHL R4
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Chapter 3 - The Processing Unit 69 240-208 Fundamental of Computer Architecture Perform instruction ADD R1,R2 MAR <= PC ADDRESS_BUS<= MAR, read MDR<= MEMORY[MAR] IR<= MDR Z<= PC + 4 PC<= Z Y<= R1 Z<= Y + R2 R2<= Z Fetch phase Execution phase
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform instruction ADD R1,R2 MAR <= PC ADDRESS_BUS<= MAR, read MDR<= MEMORY[MAR] IR<= MDR Z<= PC + 4 PC<= Z Y<= R1 Z<= Y + R2 R2<= Z Fetch phase Execution phase](http://images.slideplayer.com/37/10703440/slides/slide_69.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform instruction ADD R1,R2 MAR <= PC ADDRESS_BUS<= MAR, read MDR<= MEMORY[MAR] IR<= MDR Z<= PC + 4 PC<= Z Y<= R1 Z<= Y + R2 R2<= Z Fetch phase Execution phase")
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Chapter 3 - The Processing Unit 70 240-208 Fundamental of Computer Architecture Perform instruction ADD R1,R2 MAR <= PCPC out, MAR in ADDRESS_BUS<= MAR,read read MDR<= MEMORY[MAR]MDR inE, WMFC IR<= MDRMDR out,IR in Z<= PC + 4PC out, MUX_sel4, Add,Z in PC<= ZZ out,PC in Y<= R1Y in, R1 out Z<= Y + R2R2 out, MUX_selY, ALU Add, Z in R2<= ZZ out, R2 in Active Signals
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform instruction ADD R1,R2 MAR <= PCPC out, MAR in ADDRESS_BUS<= MAR,read read MDR<= MEMORY[MAR]MDR inE, WMFC IR<= MDRMDR out,IR in Z<= PC + 4PC out, MUX_sel4, Add,Z in PC<= ZZ out,PC in Y<= R1Y in, R1 out Z<= Y + R2R2 out, MUX_selY, ALU Add, Z in R2<= ZZ out, R2 in Active Signals](http://images.slideplayer.com/37/10703440/slides/slide_70.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform instruction ADD R1,R2 MAR <= PCPC out, MAR in ADDRESS_BUS<= MAR,read read MDR<= MEMORY[MAR]MDR inE, WMFC IR<= MDRMDR out,IR in Z<= PC + 4PC out, MUX_sel4, Add,Z in PC<= ZZ out,PC in Y<= R1Y in, R1 out Z<= Y + R2R2 out, MUX_selY, ALU Add, Z in R2<= ZZ out, R2 in Active Signals")
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Chapter 3 - The Processing Unit 71 240-208 Fundamental of Computer Architecture How to modify FETCH operation to be faster MAR <= PC ADDRESS_BUS <= MAR, Read MDR <= MEMORY[MAR], WMFC IR <= MDR Z <= PC + 4 PC <= Z MAR<= PC, Read, Z <= PC+4, PC<= Z, WMFC, MDR <= MEMORY[MAR] IR<= MDR
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture How to modify FETCH operation to be faster MAR <= PC ADDRESS_BUS <= MAR, Read MDR <= MEMORY[MAR], WMFC IR <= MDR Z <= PC + 4 PC <= Z MAR<= PC, Read, Z <= PC+4, PC<= Z, WMFC, MDR <= MEMORY[MAR] IR<= MDR](http://images.slideplayer.com/37/10703440/slides/slide_71.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture How to modify FETCH operation to be faster MAR <= PC ADDRESS_BUS <= MAR, Read MDR <= MEMORY[MAR], WMFC IR <= MDR Z <= PC + 4 PC <= Z MAR<= PC, Read, Z <= PC+4, PC<= Z, WMFC, MDR <= MEMORY[MAR] IR<= MDR")
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Chapter 3 - The Processing Unit 72 240-208 Fundamental of Computer Architecture Modified FETCH operation MAR<= PC, Read, Z <= PC+4 PC<= Z, WMFC, MDR <= MEMORY[MAR] IR<= MDR PCout, MARin, Read, Mux_sel4, Add, Zin Zout, PCin, Yin, WMFC, MDRin_f_databus MDRout, IRin Active Signals
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Modified FETCH operation MAR<= PC, Read, Z <= PC+4 PC<= Z, WMFC, MDR <= MEMORY[MAR] IR<= MDR PCout, MARin, Read, Mux_sel4, Add, Zin Zout, PCin, Yin, WMFC, MDRin_f_databus MDRout, IRin Active Signals](http://images.slideplayer.com/37/10703440/slides/slide_72.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Modified FETCH operation MAR<= PC, Read, Z <= PC+4 PC<= Z, WMFC, MDR <= MEMORY[MAR] IR<= MDR PCout, MARin, Read, Mux_sel4, Add, Zin Zout, PCin, Yin, WMFC, MDRin_f_databus MDRout, IRin Active Signals")
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Chapter 3 - The Processing Unit 73 240-208 Fundamental of Computer Architecture Perform instruction LD R1,[R2] MAR <= PC, Read, Z <= PC+4 PC <= Z, WMFC, MDR <= MEMORY[MAR] IR <= MDR MAR <= R2 ADDRESS_BUS<= MAR, MDR <= MEMORY[MAR] R1<= MDR Fetch phase Execution phase
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform instruction LD R1,[R2] MAR <= PC, Read, Z <= PC+4 PC <= Z, WMFC, MDR <= MEMORY[MAR] IR <= MDR MAR <= R2 ADDRESS_BUS<= MAR, MDR <= MEMORY[MAR] R1<= MDR Fetch phase Execution phase](http://images.slideplayer.com/37/10703440/slides/slide_73.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform instruction LD R1,[R2] MAR <= PC, Read, Z <= PC+4 PC <= Z, WMFC, MDR <= MEMORY[MAR] IR <= MDR MAR <= R2 ADDRESS_BUS<= MAR, MDR <= MEMORY[MAR] R1<= MDR Fetch phase Execution phase")
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Chapter 3 - The Processing Unit 74 240-208 Fundamental of Computer Architecture Three-bus organization
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Chapter 3 - The Processing Unit 75 240-208 Fundamental of Computer Architecture Perform Instruction ADD R6,R5, R4 on 3-bus datapath StepAction 1PC out, R=B, MAR in, Read, incPC 2WMFC, MDR in_from_databus 3MDR out_busB, R= B, IR in 4R4 out_busB, R5 out_busA, ALU ADD, R6 in, End
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Chapter 3 - The Processing Unit 76 240-208 Fundamental of Computer Architecture Control Units 2 types of Control units Hardwired Microprogrammed
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Chapter 3 - The Processing Unit 77 240-208 Fundamental of Computer Architecture Control sequence for instruction LD R1,R3 StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC, MDR in_from_databus 3MDR out, IR in 4R3 out, R1 in, End
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Chapter 3 - The Processing Unit 78 240-208 Fundamental of Computer Architecture Control sequence for instruction LD R1,[R3] StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC, MDR in_from_databus 3MDR out, IR in 4R3 out, MAR in, Read 5MDR in_f_databus,WMFC 6MDR out, R1 in, End
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Control sequence for instruction LD R1,[R3] StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC, MDR in_from_databus 3MDR out, IR in 4R3 out, MAR in, Read 5MDR in_f_databus,WMFC 6MDR out, R1 in, End](http://images.slideplayer.com/37/10703440/slides/slide_78.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Control sequence for instruction LD R1,[R3] StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC, MDR in_from_databus 3MDR out, IR in 4R3 out, MAR in, Read 5MDR in_f_databus,WMFC 6MDR out, R1 in, End")
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Chapter 3 - The Processing Unit 79 240-208 Fundamental of Computer Architecture Control sequence for instruction LD Ry,#data StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4 Offset-field-of-IR out, Ry in, End
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Chapter 3 - The Processing Unit 80 240-208 Fundamental of Computer Architecture Control sequence for STORE [Ry],Rx instruction StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Ry out, MAR in 5Rx out, MDR in_f_internalbus 6Write, WMFC, End
![Chapter 3 - The Processing Unit Fundamental of Computer Architecture Control sequence for STORE [Ry],Rx instruction StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Ry out, MAR in 5Rx out, MDR in_f_internalbus 6Write, WMFC, End](http://images.slideplayer.com/37/10703440/slides/slide_80.jpg "Chapter 3 - The Processing Unit Fundamental of Computer Architecture Control sequence for STORE [Ry],Rx instruction StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Ry out, MAR in 5Rx out, MDR in_f_internalbus 6Write, WMFC, End")
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Chapter 3 - The Processing Unit 81 240-208 Fundamental of Computer Architecture Control sequence for instruction ADD R1,R3 StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4R1 out, Y in 5R3 out, SelectY, ALU ADD, Z in 6Z out, R1 in, End
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Chapter 3 - The Processing Unit 82 240-208 Fundamental of Computer Architecture Control sequence for instruction SUB R1,R3 StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4R1 out, Y in 5R3 out, SelectY, ALU SUB, Z in 6Z out, R1 in, End
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Chapter 3 - The Processing Unit 83 240-208 Fundamental of Computer Architecture Control sequence for instruction AND R1,R3 StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4R1 out, Y in 5R3 out, SelectY, ALU AND, Z in 6Z out, R1 in, End
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Chapter 3 - The Processing Unit 84 240-208 Fundamental of Computer Architecture Control sequence for instruction OR Ry,Rx StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Ry out, Y in 5Rx out, SelectY, ALU OR, Z in 6Z out, Ry in, End
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Chapter 3 - The Processing Unit 85 240-208 Fundamental of Computer Architecture Control sequence for instruction COMPARE Ry,#data StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4 Offset-field-of-IR out, Y in 5Ry out, SelectY, ALU sub, End
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Chapter 3 - The Processing Unit 86 240-208 Fundamental of Computer Architecture Control sequence for instruction Branch rel StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Offset-field-of-IR out, ALU ADD, Z in 5Z out, PC in, End
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Chapter 3 - The Processing Unit 87 240-208 Fundamental of Computer Architecture Control sequence for instruction Branch M,rel StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Offset-field-of-IR out, ALU ADD, Z in, if Neg_F=0 then End 5Z out, PC in, End
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Chapter 3 - The Processing Unit 88 240-208 Fundamental of Computer Architecture Control sequence for instruction Branch Z,rel StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Offset-field-of-IR out, ALU ADD, Z in, if Z_F=0 then End 5Z out, PC in, End
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Chapter 3 - The Processing Unit 89 240-208 Fundamental of Computer Architecture Control sequence for instruction Branch NZ,rel StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Offset-field-of-IR out, ALU ADD, Z in, if Z_F=1 then End 5Z out, PC in, End
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Chapter 3 - The Processing Unit 90 240-208 Fundamental of Computer Architecture Control sequence for instruction INC R3 StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4R3 out, ALU INCREMENT, Z in 6Z out, R3 in, End
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Chapter 3 - The Processing Unit 91 240-208 Fundamental of Computer Architecture Control sequence for instruction Invert R3 StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4R3 out, ALU INVERT, Z in 6Z out, R3 in, End
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Chapter 3 - The Processing Unit 92 240-208 Fundamental of Computer Architecture Control sequence for instruction SHL R3 StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4R3 out, ALU SHIFTLEFT, Z in 6Z out, R3 in, End
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Chapter 3 - The Processing Unit 93 240-208 Fundamental of Computer Architecture Hardwired Control Unit
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Chapter 3 - The Processing Unit 94 240-208 Fundamental of Computer Architecture Control Unit organization
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Chapter 3 - The Processing Unit 95 240-208 Fundamental of Computer Architecture Z in and END control signals Zin = T1 + (T6 ADD) + (T4 BR)+….. End = (T7 ADD) + (T5 BR) + (((T5 N)+(T4 N)) BRN)+.... Note BR = Branch instruction BRN = Branch<0 instruction N = Negative flag
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Chapter 3 - The Processing Unit 96 240-208 Fundamental of Computer Architecture Generation of Z in control signal
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Chapter 3 - The Processing Unit 97 240-208 Fundamental of Computer Architecture Generation of END control signal
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Chapter 3 - The Processing Unit 98 240-208 Fundamental of Computer Architecture Microprogrammed control unit
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Chapter 3 - The Processing Unit 99 240-208 Fundamental of Computer Architecture “Control words” stored in “Control Store” From Figure 7.15 page 430 of “Computer Organization”, 5 th edition, Carl Hamacher, McGraw Hill
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Chapter 3 - The Processing Unit 100 240-208 Fundamental of Computer Architecture จบ บทที่ 3
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