Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, AL 36849 Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, AL 36849

BIST Methods Scan-based testing Non-scan based testing Advantages: High fault coverage Disadvantages: Area & delay overhead, yield loss, large vector size and testing times Non-scan based testing Disadvantages of scan-based testing eliminated Requires sequential ATPG High test generation complexity and low fault coverages Alleviated using DFT schemes Nontrivial vector generation in BIST environment Problem definition

Proposed Method Step 1: Spectral Analysis Step 2: BIST implementation ATPG vectors analyzed in the spectral domain Prominent spectral components chosen for BIST implementation Step 2: BIST implementation Prominent spectral components combined to generate ATPG-like vectors.

Spectral Characterization of Bit-Streams w0 Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit-stream. Walsh functions form the rows of a Hadamard matrix. w1 w2 w3 H8 = 1 1 1 1 1 1 1 1 1 -1 1 -1 1 -1 1 -1 1 1 -1 -1 1 1 -1 -1 1 -1 -1 1 1 -1 -1 1 1 1 1 1 -1 -1 -1 -1 1 -1 1 -1 -1 1 -1 1 1 1 -1 -1 -1 -1 1 1 1 -1 -1 1 -1 1 1 -1 Walsh functions (order 8) w4 w5 w6 w7 Example of Hadamard matrix of order 8 time

Analyzing Bit-Streams of ATPG vectors Input 1 Input 2 . Vector 1 Vector 2 . Spectral coeffs. Bit stream Spectral Analysis 0s to -1s . . . . . Input 2 Set 1 C(i,j) i th input j th set Bit-stream of Input 2

Determining Prominent Components For input i Averaged Spectrums Set 1 . . . . Set J Averaging Component Spectrum . . . . Phases of prominent components Averaging Power Spectrum . . . . M prominent components chosen

BIST Architecture SC1 SC2 SC3 Weighted random bit-stream (W=0.5) Proportion: SC1 = 0.5 SC2 = 0.5 Proportion: SC1 = 0.25 SC2 = 0.25 SC3 = 0.5 Weighted random bit-stream (W = 0.25) Bit-stream of spectral component Noise inserted bit-stream System Clock Hold Clock Set Length Clock BIST Clock M-bit counter which divides the clock frequency repeatedly by 2 System clock Clock derived signals Clock divider 2 Holder Cellular Automata Register with AND-OR gates N-bit counter with XOR gates BIST clock Hadamard wave generator Weighted pseudo-random pattern generator 2 Spectral component synthesizer Input 1 System clock 3 BIST clock 1 To CUT Randomizer Input 2 1 Hadamard Components 1 Input 3 Weighted pseudo-random bit-streams

Number of faults detected Hadamard BIST Results Circuit Total No. of faults Number of faults detected Flex Test ATPG Random (64k vectors) Weighted Random (64k) Hadam-ard BIST (64k) Haar BIST1 (64k) Without holding With holding Without Holding With Holding s298 308 273 269 s820 850 793 414 449 744 764 777 710 s1423 1515 1443 891 1217 1449 1469 1468 s1488 1486 1446 1161 1369 1441 s5378 4603 3547 3222 3424 3288 3537 3603 3609 s9234 6927 1588 1268 1305 1293 1303 1729 1413 s15850 13863 7323 5249 6270 5847 6696 6844 5888 s38417 31180 15472 4087 4185 4803 4949 17020 4244 Equal or more faults detected than ATPG in 5 / 8 circuits Maximum faults detected in 6 / 8 circuits 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST,” in Proc. 20th International Conf. VLSI Design, 2007, pp. 485–491.

Hadamard Results Circuit FlexTest Hadamard BIST Fault Cov. (%) No. of vectors Fault coverage (%) at 64K vecs. Fault coverage (%) at 128K vecs. BIST vecs. for FlexTest ATPG cov. s298 88.64 153 757 s820 93.29 1127 91.41 91.88 (!) s1423 95.25 3882 96.90 22345 s1488 97.31 736 97.11 s5378 77.06 739 78.27 78.67 8984 s9234 22.92 15528 24.96 25.25 8835 s15850 52.82 61687 49.37 52.15 198061 s38417 49.62 55110 54.59 63.07 43240 Equal or more faults detected than ATPG in 6 / 8 circuits

With clock divider circuit Without clock divider circuit Area Overhead Circuit No. of trans. in circuit Hadamard BIST Haar BIST1 With clock divider circuit Without clock divider circuit No. of trans. % Area overhead s298 890 908 102.02 820 92.13 834 93.71 s820 1896 1472 77.64 1340 70.68 1612 85.02 s1423 4624 1637 35.40 1483 32.07 1555 33.63 s1488 4006 1069 26.68 959 23.94 1078 26.91 s5378 12840 2342 18.24 2210 17.21 2487 19.37 s9234 23356 2700 11.56 2502 10.71 2552 10.93 s15850 43696 4908 11.23 4666 10.68 4595 10.52 s38417 108808 3606 3.31 3364 3.09 2135 1.96 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST,” in Proc. 20th International Conf. VLSI Design, 2007, pp. 485–491.

Testability analysis and enhancement Improving testability RTL faults2 defined as faults on the boundary of combinational logic XOR tree connecting unobservable RTL faults Identifying untestability Sequentially untestable faults identified using single fault theorem3 2. N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Gate-Level Stuck-at Faults,” in Proc. 15th IEEE Asian Test Symp., 2006, pp. 83–88. 3. V. D. Agrawal and S. T. Chakradhar, “Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits,” IEEE Trans. Computer-Aided Design, vol. 14, no. 9, pp. 1155–1160, Sept. 1995.

Fault and Test Coverages Example circuit: s5378 XOR tree inserted to observe outputs of 49 flip-flops from a total of 179 683 faults found as sequentially untestable using single fault theorem3 Test Method Fault Coverage (%) Test Coverage (%) Without DFT With DFT FlexTest ATPG 77.05 82.22 92.80 96.55 HadamardBIST 78.27 81.23 94.27 95.38 3. V. D. Agrawal and S. T. Chakradhar, “Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits,” IEEE Trans. Computer-Aided Design, vol. 14, no. 9, pp. 1155–1160, Sept. 1995.

Conclusion Proposed a novel method for test generation for sequential circuit BIST Proposed unique circuits for mixing spectral components and noise Method detects equal or more faults than ATPG vectors in 6 out of 8 ISCAS’89 benchmark circuits Moderate area overhead compared to existing methods Performed testability analysis and enhancement on an example circuit i.e. s5378 Proposed method is flexible and adaptable Any other suitable vectors can be used instead of ATPG vectors. Any compatible transform for binary transforms can be used for spectral analysis instead of Hadamard transform.

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