Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 221 Lecture 22 Delta I DDQ Testing and Built-In Current Testing n Current limit setting n Testing time issues Delta I DDQ testing ( I DDQ ) n Built-in current testing sensors n Summary
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 222 Current Limit Setting Should try to get it < 1 A n Histogram for 32 bit microprocessor
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 223 Hewlett-Packard / Sandia Laboratories Results n HP – static CMOS standard cell, 8577 gates, 436 FF n Sandia Laboratories – 5000 static RAM tests n Reject rate for various tests: Com- pany HP San- dia Reject Rates (%) Without I DDQ With I DDQ Without I DDQ With I DDQ Neither No Scan/ Funct Scan/ No Funct Both Functional Tests Scan and Functional Tests
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 224 Failure Distribution in Hewlett-Packard Chip
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 225 % Functional Failures After 100 Hours Life Test Work of McEuen at Ford Microelectronics
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 226 Lower / Upper I DDQ Test Time Limits – McEuen (Ford)
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 227 Delta I DDQ Testing -- Thibeault n Use derivative of I DDQ at test vector as current signature I DDQ (i) = I DDQ (i) – I DDQ (i – 1) n Leads to a narrower histogram n Eliminates variation between chips and between wafers n P – probability of false test decisions
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 228 I DDQ Versus I DDQ
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 229 Difference in Histograms n A – test escapes, B – yield loss
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2210 Parameters for Estimating P def -- minimum | I DDQ | peak from active defect, g = good mean, b = bad mean Symbol P iddq gi def gi + def i 2 def Value Below P iddq Symbol P delta gd ( 0) def gd + def d 2 P delta 7.3e e e -6 Value Below -2e P iddq / P delta Dist. Param P g def b 2 Values of P for different def Values I DDQ I DDQ
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2211 Example Differential I DDQ Histogram n Better peak resolution with | I DDQ (i) |, doubles point count
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2212 I DDQ Testing Results Item R YL (yield loss ratio) R TE (test escape ratio) P (= R YL + R TE ) Gain in test quality I DDQ 4.4e e -1 P iddq = 1.8e -1 I DDQ 3.5e e -3 P delta = 5.6e -3 P iddq / P delta = 31
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2213 I DDQ Built-in Current Testing – Maly and Nigh n Build current sensor into ground bus of device-under-test n Voltage drop device & comparator Compares virtual ground V GND with V ref at end of each clock – V GND > V ref only in bad circuits Activates circuit breaker when bad device found
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2214 Conceptual BIC Sensor
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2215 CMOS BIC Sensor
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2216 Setting Optimal # Transistors in Block n Must partition chip into functional units, each with its own BIC Too large a unit – combined leakage currents erroneously trigger BIC sensor n I defmin – smallest defect current n I noisemax – maximum noise-related peak supply current n Minimum area sensor design at I defmin and I DDQ intersection n N max – maximum # transistors in 1 BIC unit
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2217 Graph for Choosing N max
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2218 Summary n I DDQ current limit setting to differentiate between good and bad circuits is difficult n I DDQ testing is becoming more problematic Greater leakage currents in MOSFETs in deep sub-micron technologies Harder to discriminate elevated I DDQ from 100,000 transistor leakage currents I DDQ holds promise to alleviate problems n Built-in current testing holds promise