Boot Issues Processor comparison TigerSHARC multi-processor system Blackfin single-core

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 2 / 22 Overview Had planned to spend 20 minutes on boot issues on processor systems However, TigerSHARC boot involved so many different aspects of the processor and special instructions that decided to examine in more detail You will be building a multi-core boot sequence as part of Lab. 4

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 3 / 22 Information can be found at Analog Web site Analog Devices Loader Manual and various Engineer to Engineer application and technical notes Manuals manuals/index.html manuals/index.html Application Notes plicationNotes/index.html Technical articles hnicalArticles/index.html

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 4 / 22 Blackfin ADSP-BF533 “Conventional approach” What does “booting” the processor require and why is it necessary? On power up, the processor “knows” nothing. Need a systematic and reliable mechanism to “configure” the system. Essentially put registers into known state Move code from an external (8-bit wide) EPROM or FLASH memory to faster memory for easier execution Jump to the new code

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 5 / 22 How the processor “boots” is determined by “hard” settings Powers up as 0 Hard-wired

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 6 / 22 Here boot procedure starts with code from “on chip” boot rom

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 7 / 22 How do you “put” the information into the “Flash” Use VDSP to build an “executable” and “test” it Switch project option to be “loader”. This “build” option breaks the “.dxe” into blocks – “.ldr” file (in Debug) Blocks for characters Blocks for empty arrays (set to 0) Blocks for full arrays (not set to 0) Program code for “internal” memory Program code for “external” memory (SDRAM) Boot “block” – first section of code than runs

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 8 / 22 How do you “put” the information into the “Flash” Once “.ldr” loader file built, you use “Tools | Flash Programmer” to download a special program into Blackfin (TigerSHARC) This program, running on the Blackfin, burns the code into FLASH Disconnect VDSP and “reset the processor” The processor now boots

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 9 / 22 Step 1 – set PC to 0xEF and Jump (PC)

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 10 / 22 Step 2 On-board boot ROM, configures important registers Performs DMA transfer from (8 or 16 bit wide – slow speed) FLASH to on- board SCRATCH memory Must go to “scratch memory” otherwise the new downloaded code might over write old downloaded code

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 11 / 22 Step 3 Boot code is used to examine the “10 –byte header” of downloaded block Block body (in most cases)

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 12 / 22 Step 4 – Handle block based on flag information

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 13 / 22 If zero fill block shown in flags – then boot ROM code does Set address register to address (first 4 bytes of header) Set counter (second 4 bytes in memory) Using pseudo-TigerSHARC syntax LC0 = count J0 = address XR0 = 0 Loop: if nlco0e, jump Loop, [J0 += 1] = XR0 Get next header

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 14 / 22 If non zero fill block shown in flags – then boot ROM code does Set DMA destination register to address (first 4 bytes of header) Set DMA destination counter (second 4 bytes in memory) Set DMA destination stride register to 4 Set DMA source register to next address in FLASH Set DMA source counter to count (bytes) Set DMA source stride to 2 (if 16-bit flash) Set up DMA interrupt routine to set “done-flag” Activate DMA Wait till “done” Process next block

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 15 / 22 If init block shown in flags – then boot ROM code does Set DMA destination register to address (first 4 bytes of header) Set DMA destination counter (second 4 bytes in memory) Set DMA destination stride register to 4 Set DMA source register to next address in FLASH Set DMA source counter to count (bytes) Set DMA source stride to 2 (if 16-bit flash) Set up DMA interrupt routine to set “done-flag” Activate DMA Wait till “done” Set PC to address (first 4 bytes of header) and JUMP PC – system now boots

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 16 / 22 Problem – Catch 22 It is very likely that the application code is “too big” to fit into internal Blackfin Memory But you can’t write “blocks” of code in SDRAM as the SDRAM is not “configured” to accept data after power up You can’t put the configuration code in on- board ROM as you don’t know what SDRAM will be used by the system

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 17 / 22 Two stage boot-process – stage 1 “Init code” executes then returns to Boot ROM Init block runs and configures SDRAM

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 18 / 22 Make sure that you don’t destroy the boot ROM register values

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 19 / 22 This code configures the SDRAM Recover Boot ROM register values If change R0 (return value) then can cause loader to “select” which executable is to be downloaded “multi-code” boot return to boot loader

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 20 / 22 Step 2 – Boot ROM code can now load code into SDRAM

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 21 / 22 Some issues – How do you handle BF561 – multi-core processor? Build 2.dxe’s – one for each core Build a loader “file” with new boot loader.dxe as “init” block core A. dxe core B.dxe On-chip boot rom – downloads “new loader” to special memory location, and then runs the code New loader is responsible for putting code and data arrays as required

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 22 / 22 Other boot approaches Flash memory 16 bit data bus 32 bit address bus Various control logic lines Minimal approach – 4 wires -- SPI interface Chip select Clock Master out – Slave In Master in – Slave out

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 23 / 22 Other boot approaches

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 24 / 22 Speed of booting over 1 line 16 times slower than over 16 plus “clock speed issues” Flash memory 16 bit data bus 32 bit address bus Various control logic lines Minimal approach – 4 wires -- SPI interface Chip select Clock Master out – Slave In Master in – Slave out

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 25 / 22 What type of SPI memory?

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 26 / 22 TigerSHARC Boot Multi-processor system, but only 1 boot FLASH How do you handle bus contention? Does having “on-chip” boot ROM (like Blackfin) make any sense? TigerSHARC not very good at handling the bit patterns in the “field” of the block header – need to understand special TigerSHARC bit pattern instructions (extract instructions

6/1/2015Blackfin Boot, Copyright M. Smith, ECE, University of Calgary, Canada 27 / 22 Overview Had planned to spend 20 minutes on boot issues on processor systems However, TigerSHARC boot involved so many different aspects of the processor and special instructions that decided to examine in more detail You will be building a multi-core boot sequence as part of Lab. 4