1. Lab. 4 – Part 2 Demonstrating and understanding multi-processor boot
TigerSHARC multi-processor system

2. Overview
Lab. 4 Task 1– Generating and testing tasks for a multi-processor system
Lab. 4 Task 2 – Demonstrating multi-processor boot
Lab. 4 Task 3 -- Read the flags (button) from each processor and deactivate the sound from that processor (FLAG0_A deactivates left channel – FLAG0_B deactivate right channel)
Understanding new TigerSHARC functionality
Understanding TigerSHARC multi-processor bus arbitration
Understanding TigerSHARC boot-process
2/24/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

3. Bus Arbitration
We have two processors accessing one external memory location (for both read and there is no conflict.
How does the bus arbitration work on the TigerSHARC
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

4. From TigerSHARC hardware manual
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

5. Multi- TigerSHARC cluster Each processor has hard-wired ID
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

6. 2/24/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

7. 2/24/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

8. Understanding the other new instructions used during TigerSHARC boot
Copy the boot file directory into Lab4\LeftCodeDirectory
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

9. Why CJMP (NP) branches? Cache Thrash
Do we want “return addresses” stored in BTB
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

10. 2/24/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

11. FEXT instruction
As with Blackfin, TigerSHARC EEPROM has a header for each block
Need to understand block format
During boot sequences – DMA activity causes the header to be stored at memory location 0
Can access file: XR2 = [J0 += 0];; instruction
Access destination: j0 = [J31 + 1];;
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

12. FEXT – field extraction
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

13. XR3 = (0x5 << 8) | 8;; XR4 = 0x0000 1234;; XR5 = FEXT R4 BY R3;;
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

14. How does DMA work on TigerSHARC? Why so much DMA activity in boot?
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

15. Allowed DMA activity Note an important exception
This restriction explains one of the issues about the load
Process
See later
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

16. DMA 4 registers Where to start 1 D transfer info 2 D transfer info
If not 0, where the next DMA information (4 memory locations) is stored – auto DMA
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

17. DMA channels that are available on the TigerSHARC
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

18. DMA activity “during” boot load
Setting up register groups XR3:0 and XR7:4 in this part of the code
Getting processor ID is needed during boot sequence
2/24/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

19. DMA code and ISR NEW TigerSHARC instruction “idle”
Essentially “wait here” till an interrupt occurs
Loading the TCB using XR3:0 and XR7:4 causes the DMA to start
Code waits for DMA interrupt completion and then gets ready for next
Unanswered questions
How does the processor know that this was the interrupt routine to use and not another one?
Even more important – how did ANY code get into the processor?
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

20. We know what info we need to know So look in manual for detail
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

21. 2/24/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

22. Understanding the boot load
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

23. That’s where all the code came from!
One question answered
On power up, the processor automatically configures its internal registers to cause a DMA from the EPROM into its memory
That’s where all the code came from!
2/24/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

24. Boot details 1 – register config
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

25. Boot details 2 – note unknown instruction RDS – means what?
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

26. Boot detail 3 – already examined
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

27. Boot detail 4
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

28. Final stage – self modifying code to make sure system is in the correct state
Boot loader – down loads final header
Finds that it is “final block”
DMA’s “first 4 instructions” into memory and then copies those into XR registers
Replaces “first 4 instructions” with patch code
Resets DMA interrupt vector to 0x00 so that on DMA completion runs “patch code”
Starts DMA for instruction 5 to 256
Runs patch on DMA completion – which clears DMA interrupt level, restores true “first 4 instructions” and then executes
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

29. Understanding Final init procedure
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

30. Final Boot PIPELINE ISSUES 2/24/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

31. Overview
Lab. 4 Task 1– Generating and testing tasks for a multi-processor system
Lab. 4 Task 2 – Demonstrating multi-processor boot
Lab. 4 Task 3 -- Read the flags (button) from each processor and deactivate the sound from that processor (FLAG0_A deactivates left channel – FLAG0_B deactivate right channel)
Understanding new TigerSHARC functionality
Understanding TigerSHARC multi-processor bus arbitration
Understanding TigerSHARC boot-process
2/24/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada