© H. Heck 2008Section 4.11 Module 4:Metrics & Methodology Topic 1: Synchronous Timing OGI EE564 Howard Heck

Synchronous Timing EE 564 © H. Heck 2008 Section 4.12 Where Are We? 1.Introduction 2.Transmission Line Basics 3.Analysis Tools 4.Metrics & Methodology 1.Synchronous Timing 2.Signal Quality 3.Source Synchronous Timing 4.Recovered Clock Timing 5.Design Methodology 5.Advanced Transmission Lines 6.Multi-Gb/s Signaling 7.Special Topics

Synchronous Timing EE 564 © H. Heck 2008 Section 4.13 Contents Synchronous Memory Elements  Operation  Timing Requirements Bus Operation Clock Skew & Jitter Timing Analysis – Setup and Hold Manufacturability Considerations System Timing Equations Summary

Synchronous Timing EE 564 © H. Heck 2008 Section 4.14 Synchronous Memory Elements - Operation Operation A data signal (in) that is present at the input to the flip-flop is “latched” into the flip-flop by the rising edge of the input clock signal (clk). On the next rising edge of clk, the data signal is released to the output of the flip-flop (out).

Synchronous Timing EE 564 © H. Heck 2008 Section 4.15 Synchronous Memory Elements - Timing Timing Valid data must be present for a minimum amount of time prior to the input clock edge to guarantee successful capture of the data. This is setup time, T setup. Data must remain valid for a minimum amount of time after the input clock edge to guarantee that the proper value is captured. This is the hold time, T hold.

Synchronous Timing EE 564 © H. Heck 2008 Section 4.16 Synchronous Bus Operation We use the clock to control the transmission of data from the latch in the source (a) to the latch in the destination (b). clk D Q CLK D Q ab FROM CORE TO CORE We have 1 full clock cycle to get the data from a to b. The next clock pulse causes the destination latch to capture the data that was transmitted on the interconnect The initial clock pulse causes the source latch to release the data onto the interconnect.

Synchronous Timing EE 564 © H. Heck 2008 Section 4.17 Synchronous Signaling Sequence 1.Initial (driving) clock pulse transmission from clock generator to source. clk D Q CLK D Q ab FROM CORE TO CORE T drv_clk (a) (1a) T prop_clk (a) (1b) a)T drv_clk (a) = delay of the clock buffer circuit connected to the source (a). b)T prop_clk (a) = delay of the interconnect that between clk & a. A

Synchronous Timing EE 564 © H. Heck 2008 Section 4.18 Synchronous Signaling Sequence 2.Data transmission from source to destination. clk D Q CLK D Q ab FROM CORE TO CORE T drv_clk (a) (1a) T prop_clk (a) (1b) T drv (2a) T prop (2b) T setup (2c) a)T drv = delay of the output buffer circuit for the data signal. b)T prop = interconnect delay between source and destination. c)T setup = delay of the input buffer plus the flip-flop setup requirement. A A

Synchronous Timing EE 564 © H. Heck 2008 Section 4.19 Synchronous Signaling Sequence 3.Second (receiving) clock pulse transmission from clock generator to destination. clk D Q CLK D Q ab FROM CORE TO CORE T drv_clk (a) (1a) T prop_clk (a) (1b) T drv (2a) T prop (2b) T setup (2c) T drv_clk (b) (3a) T prop_clk (b) (3b) a)T drv_clk (b) = delay of the clock buffer circuit connected to b. b)T prop_clk (b) = delay of the interconnect between clk & b. A B A

Synchronous Timing EE 564 © H. Heck 2008 Section Clock Skew What happens if the clock signals at the source and destination are not in phase?  What if the clock arrives at the destination before it reaches the source? Vice-versa? What are the sources of uncertainty in the phase relationship between different clock signals?

Synchronous Timing EE 564 © H. Heck 2008 Section Clocks Skew Clock Skew: pin-to-pin variation in the timing of input clock at each agent (source & destination, in our example) on a bus. The net effect of clock skew is that it can  reduce the total delay that signals are allowed to have for a given frequency target.  require larger minimum signal delays in order to avoid logic errors. (We’ll cover this in more detail shortly.) Clock skew is caused by:  variation between the clock driver circuits in a given part ( T drv ).  variation in the loading between different agents on the bus ( C L ).  variation in interconnect characteristics ( Z 0,  d ). A B A Z 0,  d Z 0,  d CLCL CLCL T drv Clock Driver b a

Synchronous Timing EE 564 © H. Heck 2008 Section Clock Jitter What it is: Cycle-to-cycle variation in the clock period. IDEALJITTERACTUAL T cycle - T jitter T cycle + T jitter T cycle T + T jitter T cycle - T jitter T cycle - T jitter Pulse Width (Ideal) Pulse Width (Actual)

Synchronous Timing EE 564 © H. Heck 2008 Section Clock Jitter – Causes & Effects The net effect of clock jitter is that it can reduce the total delay that signals are allowed to have for a given frequency target.  i.e. jitter can reduce the clock cycle time, as illustrated by the diagrams on the previous page. Clock jitter is caused by:  noise in the system that affects the response of the clock driver circuits.  noise in the system that affects the transmission characteristics of the signals. Since they affect the operation we must consider clock skew and jitter in our timing analysis. A B A

Synchronous Timing EE 564 © H. Heck 2008 Section Skew & Jitter Example 100 MHz bus  Min clock period = 10 ns Given:  Max skew = 250 ps  Max edge-edge jitter = 250 ps. A B 0.25 ns 10 ns 9.5 ns Calculate the minimum effective clock period:  minimum effective period = minimum period – maximum skew – maximum jitter  min effective period = 10.0 ns – 0.25 ns – 0.25 ns = 9.5 ns Therefore, maximum allowed for silicon plus interconnect delay is 9.5 ns.

Synchronous Timing EE 564 © H. Heck 2008 Section Setup Timing We need to constrain the data delay such that it makes the trip from source to destination in time to meet setup requirements – while accounting for clock uncertainty. For a rigorous derivation see Appendix A. A B B A T drv T prop T skew T setup T jitter T cycle [4.1.1]

Synchronous Timing EE 564 © H. Heck 2008 Section Hold Timing We need to constrain the data delay such that it does not arrive at the destination until the hold requirement is met – while accounting for clock uncertainty. A B B A T drv T prop T hold T skew [4.1.2]

Synchronous Timing EE 564 © H. Heck 2008 Section Manufacturability Considerations Sources of variability in silicon:  manufacturing process (e.g. silicon gate length)  operating temperature (MOS speed  as temp  )  operating voltage (MOS speed  as voltage  ) Impact: variability leads to a range of values for driver and receiver timings Example: Pentium® Pro GTL+ timings  Minimum driver valid delay = 0.55 ns  Maximum driver valid delay = 4.40 ns  Maximum receiver setup time = 2.20 ns  Maximum receiver hold time = 0.45 ns Sources of interconnect variability:  Manufacturing variation ( Z 0,  r )  Trace length variation (e.g. 144 signals for FSB)

Synchronous Timing EE 564 © H. Heck 2008 Section Revised Timing Equations The setup equation defines the minimum clock cycle time (max frequency) in terms of the maximum system delay terms. We want T margin_setup  0.  Excessive system delays can be handled by increasing cycle time, at the cost of reduced performance. The hold equation defines minimum system delay requirements to avoid logic errors due to hold violations. We want T margin_hold  0.  Minimum delay violations cannot be fixed by increasing cycle time. Why? Product specifications must comprehend the expected variation. We need to modify the setup & hold equations: Setup Hold [4.1.3] [4.1.4]

Synchronous Timing EE 564 © H. Heck 2008 Section Example: Pentium® II Processor 100 MHz Host Bus Timings

Synchronous Timing EE 564 © H. Heck 2008 Section Synchronous Timing Summary Synchronous memory elements require a stable data signal for a minimum amount of time prior to (SETUP) & after (HOLD) the input clock. Hold and setup conditions determine the minimum and maximum system delays. Setup and hold conditions can be analyzed by constructing timing loops in the timing diagrams. Component delays exhibit variation across process and environmental conditions. Interconnect delays contain variations due to design and process. Redefining driver and interconnect delays in terms of system and “spec” loads allows manufacturers to specify and test component delays. System timing equations provide a key tool for examining trade- offs during system design.

Synchronous Timing EE 564 © H. Heck 2008 Section References S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1 st edition. W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, R. Poon, Computer Circuits Electrical Design, Prentice Hall, 1 st edition, H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, PTR Prentice Hall, S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley and Sons, New York, 1998.

Synchronous Timing EE 564 © H. Heck 2008 Section Appendix A: T co & Flight Time Return to main contents.

Synchronous Timing EE 564 © H. Heck 2008 Section Device Specs and Test Loads Device specifications vs. system conditions  The manufacturer guarantees that the parts meet the values in the timing specifications when driving into the “spec load”.  The spec load is typically equal to the load presented to the device by the test environment.  This spec load is generally not the same as the load presented to the device by the system interconnect. 65  10pF Spec LoadSystem

Synchronous Timing EE 564 © H. Heck 2008 Section Impact of Spec Loads Since the spec load is NOT equal to the load on the device when placed in a system:  An output buffer will have a different delay in the system than in the test environment. To deal with this:  define new timing terms &  change the way we break the timings into separate components.

Synchronous Timing EE 564 © H. Heck 2008 Section Flight Time Time Voltage Threshold Clock Input to Transmitting Chip Driver Pin into Test Load Driver Pin into System Load Receiver Pin T drv T prop T co T flight

Synchronous Timing EE 564 © H. Heck 2008 Section Define T co (time from clock-in to data-out) as the delay from the input clock to the output data when driving into the test load. Define T flight (flight time) as the delay to the receiver minus the T co.  By defining the timings in this way, the flight time accounts for the propagation delay of the interconnect PLUS the difference between the driver delays when driving test load vs. the system load. Flight Time Explained Notice:  We defined T co and T flight this way to guarantee the overall system timings remain the same.

Synchronous Timing EE 564 © H. Heck 2008 Section Another Perspective Problem: Solution:

Synchronous Timing EE 564 © H. Heck 2008 Section Revised Timing Equations The system designer relies on the synchronous timing equations help her/him define the working flight time window (min-to-max), given the component timing specs. Ultimately, the equations provide a tool for the bus design team.  Use them to evaluate design trade-offs in order to achieve system performance (frequency) targets. Setup Hold [4.1.5] [4.1.6]

Synchronous Timing EE 564 © H. Heck 2008 Section Appendix B: Synchronous Timing Equation Derivations Return to main contents.

Synchronous Timing EE 564 © H. Heck 2008 Section Setup Timing Diagram & Loop Analysis clk input T prop_clk (a) T drv_clk (a) T cycle clk output t b a clk output b a T drv T prop T margin T jitter T prop_clk (b) T drv_clk (b) T setup [4.1.1a] Return to main contents.

Synchronous Timing EE 564 © H. Heck 2008 Section Setup Timing Equation Define  Clock Delay Setup equation Simplify [4.1.1a] [4.1.2a] [4.1.3a] [4.1.4a] –Clock Skew Return to main contents.

Synchronous Timing EE 564 © H. Heck 2008 Section a Hold Timing Diagram & Loop Analysis T drv_clk (b) T prop_clk (b) T drv_clk (a) T prop_clk (a) T prop T drv a clk output clk input clk output b T margin_hold T hold t Return to main contents.

Synchronous Timing EE 564 © H. Heck 2008 Section Hold Timing Equation Hold equation Define  Clock Delay Simplify  Clock Skew [4.1.5a] [4.1.6a] [4.1.7a] [4.1.8a] Return to main contents.