1. Advanced Computer Architecture Lecture 7
Bus analysis
DC and AC
Lillevik s06-l7
University of Portland School of Engineering

2. Project 2 team reviews Team Cat Team Dog Lillevik 437s06-l7
University of Portland School of Engineering

3. System view of a computer
···
Agent 0
Agent n
···
Signal 0
Signal n

Bus
One agent at-a-time owns the bus
Lillevik s06-l7
University of Portland School of Engineering

4. Bus analysis DC AC Checks static conditions
Review high and low logic levels AC
Checks dynamic conditions
All flip-flops must meet setup and hold times
Lillevik s06-l7
University of Portland School of Engineering

5. VH drops and VL increases with greater current
DC analysis
Driver outputs
High: source current
Low: sink current
Receiver inputs
High: sink current
Low: source current
VH drops and VL increases with greater current
Lillevik s06-l7
University of Portland School of Engineering

6. Load current N Driver Receiver(s) High Low IOH IIH IOL IIL
Lillevik s06-l7
University of Portland School of Engineering

7. Example assumptions Driver: 74LS240 Receivers: 74LS74
Lillevik s06-l7
University of Portland School of Engineering

8. Why does it sink so much current?
74LS240 data sheet
Why does it sink so much current?
Lillevik s06-l7
University of Portland School of Engineering

9. 74LS74 data sheet Lillevik 437s06-l7
University of Portland School of Engineering

10. How many loads max? Lillevik 437s06-l7
University of Portland School of Engineering

11. Driving more loads
Change/mix logic families, add logic conversion circuit
Put drivers in parallel, separate traces
Lillevik s06-l7
University of Portland School of Engineering

12. Bus timing (AC) analysis
How fast can we go?
Lillevik s06-l7
University of Portland School of Engineering

13. Problem statement Sum of all delays < clock cycle
Delays: in addition to logic
Clock skew (often largest)
Input (setup, hold)
Output (valid)
Propagation delay (ps/inch)
Margin (safety factor, 5-10%)
Lillevik s06-l7
University of Portland School of Engineering

14. Clock skew The rising edge varies across topology Bus Signal Dev 1
Dev b
Dev a
Clk-dev 1
Clk-dev 2
Tskew
The rising edge varies across topology
Lillevik s06-l7
University of Portland School of Engineering

15. Input timing Setup is typically far more critical then hold Clk In OutQ
Clk In
Out
Clk
Tsetup
Thold In
Setup is typically far more critical then hold
Lillevik s06-l7
University of Portland School of Engineering

16. Output timing It takes time for the output to change Clk In Out D Q
Tvalid
Out
It takes time for the output to change
Lillevik s06-l7
University of Portland School of Engineering

17. Propagation delay
Bus Signal
Dev 1
Dev 2
Dev b
Dev a
Driver
Receiver
Tprop
Signal-dev 1
Signal-dev 2
Delay varies with the electrical properties of the media (pcb, package, sockets, vias, etc.) and trace length
Lillevik s06-l7
University of Portland School of Engineering

18. Timing Analysis Clk In Out D Q Bus Signal Lillevik 437s06-l7
University of Portland School of Engineering

19. Example assumptions Trace impedance: 50Ω , single-ended, 1.25 ns/in
Bus lengths: 3-10 inches
Clock skew: 30 ns
74LS74 flip flops
Margin of 10%
Lillevik s06-l7
University of Portland School of Engineering

20. 74LS74 data sheet Lillevik 437s06-l7
University of Portland School of Engineering

21. 74LS74 data sheet, continued.
Lillevik s06-l7
University of Portland School of Engineering

22. Find max clock frequency?
Lillevik s06-l7
University of Portland School of Engineering

23. Another example Fmax = 10 MHz
Trace impedance: 50Ω , single-ended, 1.25 ns/in
Bus length: 5 inches
74LS74 flip flops
Margin of 5%
Lillevik s06-l7
University of Portland School of Engineering

24. Find maximum clock skew?
Lillevik s06-l7
University of Portland School of Engineering

25. High-speed bus analysis
Entire system modeled (IBIS)
Silicon  package  traces/vias  package  silicon
Electrical path a transmission line
3-D field solver (iterative)
May take hours of simulation time
Results in bus guideline document (sample design)
Lillevik s06-l7
University of Portland School of Engineering

26. Example product sheet Lillevik 437s06-l7
University of Portland School of Engineering

27. Lillevik s06-l7
University of Portland School of Engineering

28. Max load (fan-out) of ~15 devices
How many loads max?
Max load (fan-out) of ~15 devices
Lillevik s06-l7
University of Portland School of Engineering

29. Find max clock frequency?
Lillevik s06-l7
University of Portland School of Engineering

30. Find maximum clock skew?
Lillevik s06-l7
University of Portland School of Engineering