For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201- 44494-1. © 2002.

Slides:



Advertisements
Similar presentations
BEOL Al & Cu.
Advertisements

CHAPTER 8: THERMAL PROCESS (continued). Diffusion Process The process of materials move from high concentration regions to low concentration regions,
Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid. ISBN © 2006 Pearson Education, Inc.,
CMOS Fabrication EMT 251.
Lecture 0: Introduction
Process Flow Steps Steps –Choose a substrate  Add epitaxial layers if needed –Form n and p regions –Deposit contacts and local interconnects –Deposit.
Simplified Example of a LOCOS Fabrication Process
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
CMOS Process at a Glance
Chapter 2 Modern CMOS technology
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
VLSI Design Lecture 2: Basic Fabrication Steps and Layout

A Primer on CMOS Technology. Objectives: 1.To Introduce about CMOS technology.
EE143 – Ali Javey Section 8: Metallization Jaeger Chapter 7.
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
Introduction to CMOS VLSI Design Lecture 0: Introduction
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
ECE/ChE 4752: Microelectronics Processing Laboratory
Device Fabrication Example
Introduction Integrated circuits: many transistors on one chip.
CMOS Process Integration ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May March 25, 2004.
ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.
ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001.
Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.
1 VLSI Fabrication Technology. Microelectronic Circuits - Fifth Edition Sedra/Smith2 Copyright  2004 by Oxford University Press, Inc. Figure A.1 Silicon.
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Chapter 3 Solid-State Diodes and Diode Circuits
MOHD YASIR M.Tech. I Semester Electronics Engg. Deptt. ZHCET, AMU.
Figure 9.1. Use of silicon oxide as a masking layer during diffusion of dopants.
VLSI, Lecture 1 A review of microelectronics and an introduction to MOS technology Department of Computer Engineering, Prince of Songkla.
Metallization: Contact to devices, interconnections between devices and to external Signal (V or I) intensity and speed (frequency response, delay)
Taklimat UniMAP Universiti Malaysia Perlis WAFER FABRICATION Hasnizah Aris, 2008 Lecture 2 Semiconductor Basic.
Chapter 4 Overview of Wafer Fabrication
IC Process Integration
Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid. ISBN © 2006 Pearson Education, Inc.,
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 9 IC Fabrication Process Overview.
Dielectrics • Dielectrics electrically and
EE415 VLSI Design 1 The Wire [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.
© 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Semiconductor Manufacturing Technology Michael Quirk &
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.
IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.
ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.
NMOS FABRICATION 1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities.
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
©2008 R. Gupta, UCSD COSMOS Summer 2008 Chips and Chip Making Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.
VLSI INTERCONNECTS IN VLSI DESIGN - PROF. RAKESH K. JHA
Chapter13 :Metallization
1 Overview of Fabrication Processes of MOSFETs and Layout Design Rules.
Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.
Metallization materials should: physically it must:
CMOS VLSI Fabrication.
CMOS FABRICATION.
CMOS Fabrication EMT 251.
From Principles of Electronic Materials and Devices, Third Edition, S.O. Kasap (© McGraw-Hill, 2005) These PowerPoint color diagrams can only be used by.
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Manufacturing Process I
Layout and fabrication of CMOS circuits
Metallization.
Chapter 1 & Chapter 3.
Solid State Devices Fall 2011
Manufacturing Process I
Manufacturing Process I
CSE 87 Fall 2007 Chips and Chip Making
Presentation transcript:

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Introduction to Microelectronic Fabrication by Richard C. Jaeger Distinguished University Professor ECE Department Auburn University Chapter 7 Interconnections and Contacts

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Copyright Notice © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN

© 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections and Contacts MOS Logic Circuit 3 Basic Interconnection Levels –n + diffusion –Polysilicon –Aluminum Metallization Contacts –Al-n + –Al-Polysilicon –Al-p Substrate Contact Not Shown Figure 7.1 Portion of MOS integrated circuit (a) Top view (b) Cross section

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Resistivity of Metals Commonly Used Metals Aluminum Titanium Tungsten Copper Less Frequently Utilized Nickel Platinum Paladium

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Contacts Ohmic Contact Formation (a) Ideal Ohmic Contact (b) Rectifying Contact (similar to diode) (c) Practical Nonlinear “Ohmic” Contact

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Contacts Ohmic Contact Formation Figure 7.3 Aluminum to p-type silicon forms an ohmic contact similar to Fig. 7.2(a) [Remember Al is p-type dopant] Aluminum to n-type silicon can form a rectifying contact (Schottky barrier diode) similar to Fig. 7.3(b) Aluminum to n+ silicon yields a contact similar to Fig. 7.3c Figure 7.2

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Contacts Aluminum-Silicon Phase Diagram Aluminum-Silicon Eutectic Point 577 o C

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Contacts Aluminum Spiking and Junction Penetration Silicon absorption into the aluminum results in aluminum spikes Spikes can short junctions or cause excess leakage Barrier metal deposited prior to metallization Sputter deposition of Al - 1% Si

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Contacts Alloying of Contacts

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Contacts Contact Resistance

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Electromigration (a) (b) High current density causes voids to form in interconnections “Electron wind” causes movement of metal atoms

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Electromigration Copper added to aluminum to improve lifetime (Al, 4% Cu, 1% Si) Heavier metals (e. g. Cu) have lower activation energy

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Diffused Interconnections n- and p-type diffusions can be used for local interconnections pn-junction diode must be kept in its reverse-biased (non- conducting) state All interconnections have a series resistance R and shunt capacitance C per unit length The RC time constant limits operating frequency n + and polysilicon lines R S ≥ 30  /square Figure 7.9 Lumped RC model for a small section of an n+ diffusion

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Diffused Interconnection Diffused interconnection in NMOS OR gate. Merged source and drain regions used to interconnect devices Multiple contacts used to reduce overall contact resistance Figure 7.10

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Buried and Butted Contacts Techniques for interconnecting polysilicon and n+ diffusion (a)Standard metal level link (b)Buried contact with polysilicon in contact with diffusion (requires additional mask step to place n + under polysilicon (c)Butted contact with aluminum overlap Figure 7.11

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Silicides/Polycides/Salicides Silicides of noble and refractory metals can be used to reduce sheet resistance of polisilicon and diffused interconnections Provide shunting layer in parallel with original inteconnection Figure 7.12

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Properties of Various Silicides

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Salicide Self-Aligned Silicide on silicon and polysilicon Often termed “Salicide”

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Contacts Silicide Contacts in Devices

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Liftoff Process (a) Subtractive etching process (b) Additive metal liftoff process Figure 7.15

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Multilevel Metallization Two level metal processes Silicon dioxide, polyimide or silicon nitride dielectrics Vias formed to connect between metal levels Vias can be filled (b)to improve planarization Figure 7.16

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Multilevel Metallization Example of multilevel aluminum metallization with tungsten via plugs Planarity achieved through Chemical Mechanical Polishing (CMP) Figure 7.17 Multilevel aluminum metallization with tungsten plugs. Copyright 1998 IEEE. Reprinted with permission from Ref. [7]. Al

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Plated Copper Copper deposited using “standard” plating processes adapted to microelectronics Seed layer deposited Mask layer deposited and patterned Copper plated up Mask layer removed Seed layer etched away

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Copper Damascene Process Damascene process used to obtain highly planar surfaces Dielectric layer (insulator) deposited and patterned Seed layer deposited Copper plated Surface polished mechanical & chemical

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Dual Damascene Process

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections Dual Damascene Process (cont.)

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Multilevel Metallization Examples Figure 7.20 (a) Dual Damascene copper combined with aluminum- copper and tungsten plugs on the lower levels. Copyright 1997 IEEE. Reprinted with permission from Ref. [6]. (b) Dual Damsascene Copper. Courtesy of Motorola Inc. Note planarity of both structures. (a) (b)

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Interconnections and Contacts References

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. End of Chapter 7