Bump bonding follow up from AUW R. Bates & F. Hügging

Introduction/Motivation Build seems far away but need to address significant questions over the next few years Technical challenge: – Similar to IBL (see next slides) – BUT with massive volume & rate increase – ~ 7000 good modules – Module build : 2 years – Peak Flip-chip rate: 60 modules / day – Need 3 vendors with 20 modules / day minimum capacity Timescales: – TDR in 2017 – Contracts placed – Pre-production (10% level) 2018 to mid-2019 Next 2-3 years – Need a realistic expectation of what we can achieve by the TDR – Note that most of this is work before any RD53-FE full wafers 11/12/20142Richard Bates - Glasgow

Moving forward in next 3 years Need to have about 5 vendors or more to choose from Make the choice in 2017/18 By then vendors should – Demonstrate technical requirements – Demonstrate rate Perhaps at a few of the vendors if not all Maybe sufficient at this point to have commitment to rates – Give cost estimates Produce enough quads for the project – System level work – Does not need final thickness – Assembly dressing Can we wait on the new chip for this? – Perhaps not – Need a test vehicle at 300mm? More than just bump density! 311/12/2014Richard Bates - Glasgow

For today – mini-production Plan to start a common quad-module production, with the goal of testing bump-bonding vendors quality and rate capabilities. Discussion in progress to identify the best time for the production and the best way to share resources. From Paolo’s ITK-SG talk of Dec 4 th Today should not close down vendor options but use this exercise as a method to encourage development and introduce a benchmark to measure progress And encourage further vendor engagement 11/12/20144Richard Bates - Glasgow

Vendors presented at AUW IZM – SnAg solder on FEI4, Cu UBM on sensor – Thin ROIC with Temporary support wafer Selex – Indium on both sensor and FEI4 – Simple Chromium UBM – Thin, no support wafers modules produced HPK – SnAg solder on FEI4 – Thinned, no support wafers Still a few issues CEA Leti/Advacam – Copper pillars with SAC solder on FEI4 – ROIC thinning and backside compensation layer Under development – Thin UBM on sensor and flip-chip at Advacam STFC/RAL – Indium on both sensor and FEI4 – Simple Chromium UBM – Relatively early in development cycle – 4 single chip assemblies – 2015 – to early for thin quad assembly better target date 5 Maturity 11/12/2014Richard Bates - Glasgow

Bump vendor candidates - updated VendorProcessWafer-to- wafer Chip-to- wafer Chip-to- Chip Thin chipsReworkTemp. range CommentsATLAS contact IZM BerlinSolder bumps, SnAg NoYes HighUsed with Atlas Pixel F. Hügging (Bonn) EMFTSLIDYes NoYesNoHighA.Maccchiolo (Munich) RTISolder bumps ??Yes??HighUsed with CMS Pixel V. Fadeyev (St. Cruz) SelexIn bumps??Yes LowUsed with Atlas Pixel G Alimonti (Genova) CEA- Leti/ADVACAM Solder bumps ?Yes DevelopmentYesHighUsed with Alice Pixel R. Bates (Glasgow) HPKSolder bumps ??Yes Development YesHigh Y. Unno (KEK) STFCIn BumpsNo Yes Development YesLowJ. Lipp (RAL) ZiptronixDBI Oxide Bonding Yes ? NoHigh?? ZyCubeGlue injection Bonding Yes?? ??? 11/12/20146Richard Bates - Glasgow

Next slides detail bump yield and qualification process – Hopefully not too contentious as based on IBL numbers Rate – Today this will be tricky to confirm as needs a significant number of wafers Aim for 2016 for rate test We should be, at first order, blind to the process details – As long as we have confidence in the process we do not define wafer handling or Solder bonds Sensor side issues – Do we worry about 3D sensors at this moment? Surface of sensor not the same as planar & therefore might complicate matters – 8 inch CMOS planar sensors Interesting as could change vendor side constraints 11/12/2014Richard Bates - Glasgow7

Bump-bonding specs Starting point is IBL specifications Significant additional requirements – Larger area assemblies – quad 2x2 – ROIC wafer size will be 300mm compared to 200mm diameter – Rate Wish to get to a minimum of 20 modules per day flip-chip capacity Other requirements – Demonstrate with 25 x 100 um pixels – Push to thinner modules? IBL with 150um ROIC, can we go thinner? – Smaller inter-ROIC spacing? Inter-ROIC distance now many times pixel size 11/12/20148Fabian Hügging - Bonn

Bump bonding specifications updated from IBL – material: SnAg, PbSn (solder) or Indium or ?? – pitch: 50 µm in both directions – bump density: 400 per mm 2 – target chip thickness: 100 – 150 µm – maximum process temperature: 260°C – passivation opening for bump: ~12 µm – max. failure rate (bumping only) on individual bumps (shorts or missing bumps): 3 x – max. failure rate (bumping & flip-chip): 400 per 4-chip-module, 150 per chip – perfect IC bump row to sensor bump row matching (no displaced ICs) – electrostatic discharge protection required – bump uniformity on Indium bumps better than 1 µm in height before flipping – minimum bump height after flipping: 6 µm – maximum bump height after flipping: 25 µm – maximum bump diameter after flipping: 35 µm – reduces shorts – firm must specify all processing temperature cycles – tear and shear strengths of bumps: > 0.1g/bump 11/12/20149Fabian Hügging - Bonn

Bump bonding qualification process Require up to 20 prototype quad-modules from each vendor fulfilling the requirements which undergo a test program for stressing the bump connectivity: – Single and quad FE-I4 modules Stress test fine on singles, but quads required to prove full process – All modules glued to a carbon plate to mimic the situation in the detector (plus flex?) – Electrical tests of the bump bond connectivity before, during and after the stress tests. 11/12/201410Fabian Hügging - Bonn

Qualification process 1.Acceptance test of all prototype modules to ensure that the modules fulfill the requirements. 2.5 modules shall undergo a thermal cycling stress tests with following parameter: – Minimum temperature: - 40°C – Maximum temperature: +60°C – Dwell time at minimum/maximum temperature: 30min – Rise/Fall time of the temperature: > 5°C per min. – Number repetitions: 100 – 1 week operation at -40°C – Modules must be powered (low and high voltage) during the process – Electrical measurements of the bump bond connectivity at least after every 20 repetitions. 3.5 modules shall undergo a thermal shock stress test with following parameters: – Start temperature: +25°C, stop temperature: -30°C – Temperature fall time: > 6°C per sec – taken from Danilo’s stave design requirements – Number of repetitions: 100 – Electrical measurements of the bump bond connectivity at least after every 20 repetitions. 4.5 modules shall undergo long term operation tests at different temperatures: – Temperature range: at least 5 temperatures between -30°C and +40°C – Operation time at each temperature: > 24 h – Modules must be powered up the entire time and be tested electrically for bump bond connectivity at least 3 times during each temperature step. Note on temperatures: Danilo’s stave design requirements spread sheet shown at the AUW week states that the thermal load is -35C to +40C and therefore suggests a design value of -55C to +60C (20C safety factor). 11/12/201411Fabian Hügging - Bonn

Qualification criteria Increase of the defect rate: less than or 5 per chip per thermal cycle or thermal shock. In total the defect rate after all thermal cycles and shocks shall not be higher than 800 per 4-chip module or 300 per chip (2 times the defect rate after the production). The rate of new defects per thermal cycle or shock of the 2 nd half of repetitions must always be lower (within statistical significance) than the defect rate per cycle of the 1 st half of repetitions. Defect rate after long term operational tests: 600 per 4-chip module or 200 per chip. 11/12/201412Fabian Hügging - Bonn

Proposal for the way forward Full thickness wafers at CEA Leti – Full wafer thickness – Approx 1keuro per wafer – Able to start in Jan 2015 – Thin wafers wait until mid 2015 IZM – Plans? Selex – Plans? HPK – Plans? STFC – Wait until /12/2014Richard Bates - Glasgow13

BACKUP 1411/12/2014Richard Bates - Glasgow

PIX STR 2016 Pre-series Pre-series Bulk Chip Fabrication/purchase Stave & Petal Production, local Supports Barrel Integration at CERN EC Integration x 2 Bulk Sensor Fabrication Module Production Module Loading Integration Ship EC to CERN TDR The Production Years up to /12/2014 Richard Bates - Glasgow

From IDR : Timescales and volumes Assume 10 m 2 of active area (to build for 8.2m 2 installed) All quad modules = 14cm 2 -> 7200 good modules Flip-chip rate, IDR concludes : – Factoring in some yields and bunching of production Module build : 2 years Peak Flip-chip rate: 60 modules / day Need 3 vendors with 20 modules / day minimum capacity Assembly starts a little before module assembly and test 16 11/12/2014 Richard Bates - Glasgow

TDR onwards TDR in 2017 Aim to identify vendors in 2017 / early 2018 – Require sufficient information to make sensible selection Preproduction in 2018 to mid-2019 – Typically 10% level – Allows full qualification of the selected vendors – Need to do in time to sort out technical issues and speed – Breakpoints in case of major problems! – Assembly pre-production feeds into module assembly pre-production Assume – 3 vendors, 60modules/day – 850 modules (~10%) – Over 2 – 3 months duration – About 13 wafers/ vendor (148 die/300mm wafer, 60% ROIC yield) Significant number of assemblies by 2020 – Date given as start of module production and testing 17 11/12/2014 Richard Bates - Glasgow