From SRAM to DDR3 for VFC-HPC V2 Consequences and performances

From SRAM to DDR3: what would change? Memory total bandwidth reduced: from 11.5Gbps for the to 2.66Gbps (more than a factor 4) Memory storage increased: from 144Mb to 16Gb (more than a factor 100) Cost per board reduced of about 200CHF Note: 1 DDR3 at 1.33Gbps has the BW of a 16bit connected to a ARRIA V GX

DDR3 with ARRIA-V Vs. 12bit fast (400+Msps) ADC The issue: – DDR3 BW = 2.66Gbps – Data = 5.76Gbps per channel The possible solutions or compromises – Using an internal buffer and time multiplexing the acquisitions (TMX) – Data compression to a factor 2 (lossy or lossless) (CMP) – Data “rebinning” with smart algorithms to the bunch level leading to 40MHz (R2B)

Options: TMX Using an internal high speed buffer (FIFO) before the DDR3 The total memory is 15kb: reading the buffer at half the writing speed will allow us to store without loss 30kb before saturation. 30kb are 2.5ksamples or ~200 bunches (25ns slots) We could divide the accelerator in 18 batches of 198 consecutive bunches. Each turn we can acquire a subset of 9 of those and – Have a full accelerator every 2 turns (minus part of the abort gap) – Acquire for N turns half of the accelerator and the N turns after the other half – Use 2 boards to get to full rate

Options: CMP The patterns are well known and ad hoc algorithms could be studied to reduce the data rate (performance to be evaluated) Lossless compression could be used (non constant compression rate….) Lossy compression like – Wavelet compression (easy to implement in an FPGA) – Recoding like in simil-floating point. Using 4 bits to encode the exponent and 2 bits of mantissa we would introduce an error on the encoded sample of less than 12.5% even if we would use a 16bit ADC as data source (relative error is fixed)

Options: R2B With the knowledge of the pulse shape algorithms could be implemented to recover the amplitude of the pulses in the various 25ns slots even in the case of leakage of the signal into more than one slot. The signal can be in first approximation be estimated to have 16 bits starting from a 12 bit one going down to 40MHz with an equivalent BW of 640Mbps. This solution is compatible with 4 channels per VFC

Comparison TMXCMPR2B 400Msps 31k full turns Only half ring can be acquired each turn in slices of 200 bunches 62k full turns 280K turns Could be shared between 4 channels 440Msps 31k full turns Only half ring can be acquired each turn in slices of 200 bunches AG cannot be acquired in ping-pong mode 62k full turns 280K turns Could be shared between 4 channels 480Msps 31k full turns Only half ring can be acquired each turn in slices of 200 bunches AG cannot be acquired 62k full turns Requires compression factor of K turns Could be shared between 4 channels

References mem-index.jsp mem-index.jsp - memory/emi_intro_specs_select_memory.pdf - memory/emi_intro_specs_select_memory.pdf