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Dima Svirida (ITEP/BNL) Comments on Polarimeter Programming NEW IN RUN6  AGS polarimeter switched to 10 times faster readout with CMC100 USB controller.

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Presentation on theme: "Dima Svirida (ITEP/BNL) Comments on Polarimeter Programming NEW IN RUN6  AGS polarimeter switched to 10 times faster readout with CMC100 USB controller."— Presentation transcript:

1 Dima Svirida (ITEP/BNL) Comments on Polarimeter Programming NEW IN RUN6  AGS polarimeter switched to 10 times faster readout with CMC100 USB controller  RHIC polarimeters completely decoupled from each other (Blue-Yellow-HJet)  New measurement scripts developed by CAD, including target scans and polarization averaging by target movement  WFD version 10 debugged and implemented with HJet  New HJet off-line software developed allowing fast polarization result on run by run basis

2 Dima Svirida (ITEP/BNL)  Data flows and calculation algorithms are significantly changed  No direct readout – only storage of events to the onboard memory  Raw waveform modes completely removed (now HJET, AT, ALL)  HJet waveform mode introduced allowing prehistory recording and programmable waveform length up to 3.5  s  New baseline subtraction algorithm introduced:  4 points of each “no signal” waveform are averaged within the window of the bunch period  “running average” over 64 “no signal” bunches calculated  the baseline of the inverted signal is shifted 8 ADC units from zero to account for the noise and small overshoot  Separate waveform and parameters FIFO allow buffering in all modes of operation including ‘ALL’ (waveform+parameters)  Lookup tables, histograms and scales are kept the same as in V9 for fast on-line result New in WFD Version 10 ADCs 3pt filter Level trigger Baseline calc Baseline subtraction, inversion and shift To waveform recorder

3 Dima Svirida (ITEP/BNL) Data Flows in V10 Digital delay line Delay Gate Level trigger Length Waveform FIFO To memory ‘HJET’ MODE ‘AT’ AND ‘ALL’ MODES Delay 2 bunch crossings TMAX, Amplitude, Integral Backward scanTime algorithms LUT logic Gate ‘WF’ FIFO ‘AT’ FIFO To memory Delay 1 bunch Histograms  Completely different data flows in different modes, yet sharing the same FPGA resources WF enable

4 Dima Svirida (ITEP/BNL)  Based on previous test signal off-line calculations 2 best time algorithms were chosen out of 7 studied  Programmable CFD threshold ¼ or ½ of the amplitude Time Determination Algorithms CFD 3+3 points  3 points above and below threshold are averaged  Line connecting averages crossing the threshold defines the time Average leading edge  Area of the hatched figure is calculated and divided by the amplitude  The time is represented by the horizontal side of the equivalent rectangular


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