1. Ewald Effinger, Bernd Dehning 20.03.2014
BE/BI Technical board on Electronics choices for Fast (BLM) electronics
Ewald Effinger, Bernd Dehning

2. Outline Detector overview Motivation for a new Fast DAQ
Diamond Detector with Cascade Schemes (Cividec detector with copper cable)
Optical diamond detector from CMS & DESY (BCM1F4LHC)
BLMED Installation Overview
Motivation for a new Fast DAQ
Technical Specification of Fast DAQ
System propositions
Solution CERN made or outside company
FMC based system (BI development)
Tender System 1 – System 5
System Compare

3. New Diamond Detector Cascade Schemes
Detector signal split in two signal paths (direct and 40dB amplified)
Monitoring of complete dynamic range possible
No need to access tunnel to exchange amplifier for different users

4. Optical diamond detector (BCM1F4LHC)
All detector signal arrive on the same position
Easy access of data acquisition system
Lower dynamic range

5. BLMED Installation Overview
Acc IP
Position
Detector
LHC 2
BLMED.04L2.B1I10_TCTVB.4L2
CIVIDEC 3
BLMED.06L3.B1I10_TCP.6L3.B1
BLMED.06R3.B2E10_TCP.6R3.B2 6
BLMED.04L6.B2I10_TCSG.4L6.B2
BLMED.04R6.B1E10_TCSG.4R6.B1 7
BLMED.06L7.B1E10_TCHSS.6L7
BLMED.06R7.B2I10_TCHSS.6R7 8
BLMED.04R8.B2C10_TCTVB.4R8
SPS 4
MSE 41876
TPSG 61773
BLMED.04L2.B1C10_TDI.4L2.B1
BCM1F4LHC
BLMED.04R8.B2C10_TDI.4R8.B2
BLMED.05L4.B1C10_BGI
BLMED.05R4.B2C10_BGI 5
BLMED.04L5.B1I10_TCTVA.4L5.B1
BLMED.04R5.B2I10_TCTVA.4R5.B2
Following detectors are foreseen to be installed while LS1 and LS2
1 detector for Fast Servospill in the SPS TT20 (LS1)
1 detector for HiLumi in the LHC (LS1)
8 detectors for Booster dump (LS2)
12 (?) detectors for PS (LS2)

6. Motivation for a new Fast DAQ
More reliability of data acquisition in compare with windows based LeCroy Scope
Decrease rental cost for scopes
(450CHF per month and scope)
Less complicated set up for BCM1F detector
Supported and maintained by DESY
Complex data treatment structure
Single data acquisition system for both detector types
Equal readout and data treatment for both detectors

7. Technical Specification of Fast DAQ
Analogue bandwidth
DC – 500 MHz
V In min
10 mVpp
V In max
10 Vpp
 7V RMS
Acquisition:
Resolution
8/10/12 bit
 Solution specific
Sampling rate
1Gs/s (2.5ns – 1ns)
Sampling length
10ms 1Gs/s per channel
 selectable
8 bit
10k – 1G (points) = 240kbit – 24Gbit (4Gbyte)
4 Channels
12 bit
10k – 1G (points) = 360kbit – 36Gbit (
3 Channels
Trigger system:
Signal input
Edge (Threshold set with 10bit DAC)
Min. 5mV
Ext. Input 2
Edge
TTL signal
Software trigger
On event
via data transmission
Histogram:
ns (57024 bins)
 Bunch length / 16
Trigger threshold
min. 5mV
 10 bit DAC
Counter
20-24 bit per bin
Update rate 1s
Scaler:
20-24 bit
Controller or FPGA software:
Source code
User accessible for modifications
Preferable
Drivers & Control software
Driver
Open source Linux  
Control
Linux

8. System propositions 8 - 10 - 12 bit solution possible
3 – 4 channel per system needed
Splitter and/or optical input
can be separated form DAQ
In case of a modular system more than 4 channel possible
Parallel processing of Histogram and Loss versus time mode preferable

9. FMC based system (BI development)
System based on BI VFC board
Digitizer FMC board, 8/10/12 ADC 1GSPS, no memory on the board.
VME 64 create and Linux CPU needed per system
Not compatible with dead lines of project
Series production of VFC (start end of 2014)
Tender for FMC card
FPGA and CPU Software form BI needed

10. Tender System 1 Custom made MTCA 4 Channel 1.25GSPS 10bit ADC
Virtex 6 FPAG and DDR3 memory interface
FPGA software done by vendor
Create and single board computer and MCH not included (not included in the offer)
Offer not compatible with dead line
CPU software not mentioned

11. Tender System 2 3 * 1 Channel 1.6GSPS 12bit ADC
FPGA board with Kintex -7 and 2 Gbit RAM
2.3 GHz Quad-Core PXI Express Controller
8-Slot 3U PXI Express Chassis with AC - Up to 7 GB/s
Modular system, stand alone
Compatible with dead line
CPU and FPGA Software consulted by vendor

12. Tender System 3
1 * 4 Channel 1.25 GSPS 8bit ADC with Xilinx Virtex 5, 16 GB compact flash card
1 * 2 Channel 2.5 GSPS 8 bit ADC with Xilinx Virtex 5
Mother board NANO-PV-D5251with Intel Atom D GHz and 4GB RAM, Linux based software.
5 Gbit/s connection between ADC and CPU .
Compatible with dead lines
CPU and FPGA Software included in the offer

13. Tender System 4 No specified description given in the offer
New custom made development all requirements should be fulfilled
Compatible with dead lines

14. Tender System 5
1 * 4 Channel 1GSPS 12bit ADC with Virtex 6 and 1 Gbit RAM
Analogue frontend with selectable gain
Linux based CPU to connected to ADC and data treatment.
19 “ chassis, stand alone system
CPU and FPGA Software included in the offer

15. System Compare Values in grey correspond to specified values ! System
Important Technical Aspects
BI/BL Man power
Dead line
Comments
Storage per Ch
Resolution
Rate
FPGA
CPU
Production
BI/BL
8 MByte
10 bit
1 GSPS
Yes No
Tender for FMC needed
Tender 1
1.25 GByte
1.25 GSPS
Offer is without chassis and CPU
Tender 2
2 GByte
12 bit
1.6 GSPS
Modular system, Onsight consualtion
Tender 3
4 GByte
8 bit
QT GUI exist, Future option 12 bit
Tender 4
1.5 GByte
Completely new development
Tender 5
250 MByte
Future option 8 Gbyte
Values in grey correspond to specified values !