FinFETs: From Circuit to Architecture Niraj K. Jha Dept. of Electrical Engineering Princeton University Joint work with: Anish Muttreja, Prateek Mishra, Chun-Yi Lee, Ajay Bhoj and Wei Zhang

Talk Outline Background Low Power FinFET Circuits Architectural Impact Unusual Logic Styles Unusual Dual-Vdd/Dual-Vth Circuits Architectural Impact Other Ongoing Work Conclusions

Why Double-gate Transistors ? Feature size 32 nm 10 nm Bulk CMOS DG-FETs Gap Non-Si nano devices DG-FETs can be used to fill this gap DG-FETs are extensions of CMOS Manufacturing processes similar to CMOS Key limitations of CMOS scaling addressed through Better control of channel from transistor gates Reduced short-channel effects Better Ion/Ioff Improved sub-threshold slope No discrete dopant fluctuations

What are FinFETs? Fin-type DG-FET A FinFET is like a FET, but the channel has been “turned on its edge” and made to stand up Si Fin

Independent-gate FinFETs Back Gate Oxide insulation Both the gates of a FET can be independently controlled Independent control Requires an extra process step Leads to a number of interesting analog and digital circuit structures

FinFET Width Quantization Electrical width of a FinFET with n fins: W = 2*n*h Channel width in a FinFET is quantized Width quantization is a design challenge if fine control of transistor drive strength is needed E.g., in ensuring stability of memory cells FinFET structure Ananthan, ISQED’05

Talk Outline Background Low Power FinFET Circuits Architectural Impact Unusual Logic Styles Unusual Dual-Vdd/Dual-Vth Circuits Architectural Impact Other Ongoing Work Conclusions 7

Motivation: Power Consumption Traditional view of CMOS power consumption Active mode: Dynamic power (switching + short circuit + glitching) Standby mode: Leakage power Problem: rising active leakage 40% of total active mode power consumption (70nm bulk CMOS) † †J. Kao, S. Narendra and A. Chandrakasan, “Subthreshold leakage modeling and reduction techniques,” in Proc. ICCAD, 2002.

Logic Styles: NAND Gates SG-mode NAND IG-mode NAND IG-mode pull up pull up bias voltage LP-mode NAND IG/LP-mode NAND LP-mode pull down pull down bias voltage

Comparing Logic Styles Design Mode Advantages Disadvantages SG Fastest under all load conditions High leakage† (1μA) LP Very low leakage (85nA), low switched capacitance Slowest, especially under load. Area overhead (routing) IG Low area and switched capacitance Unmatched pull-up and pull-down delays. High leakage (772nA) IG/LP Low leakage (337nA), area and switched capacitance Almost as slow as LP mode †Average leakage current for two-input NAND gate (Vdd = 1.0V)

FinFET Circuit Power Optimization Construct FinFET-based Synopsys technology libraries Extend linear programming based cell selection† for FinFETs Use optimized netlists to compare logic styles at a range of delay constraints 32 nm PTM FinFET models Delay/power characterization in SPICE LP IG/LP IG SG Synopsys libraries inFET models (UFDG, PTM) Logic gate designs Benchmark Minimum-delay synthesis in Design Compiler SG-mode netlist Power-optimized mixed-mode netlists SG+ IG/LP SG+IG SG+LP Linear programming based cell selection †D. Chinnery and K. Keutzer, “Linear programming for sizing, Vdd and Vt assignment,” in Proc. ISLPED, 2005. 11

Power Consumption of Optimized Circuits Estimated total power consumption for ISCAS’85 benchmarks Vdd = 1.0V, α = 0.1, 32nm FinFETs Available modes Leakage power savings 110% a.t. (68.5%) 120% a.t. (80.3%) Total power savings 110% arrival time (a.t.) (34%) 120% a.t. ( 47.5%) 12

Talk Outline Background Low Power FinFET Circuits Architectural Impact Unusual Logic Styles Unusual Dual-Vdd/Dual-Vth Circuits Architectural Impact Other Ongoing Work Conclusions 13

Dual-Vdd FinFET Circuits Conventional low- power principle: 1.0V Vdd for critical logic, 0.7V for off-critical paths Our proposal: overdriven gates Overdriven FinFET gates leak a lot less! Reverse bias Vgs=+0.08V Higher Vth 1.08V 1V Leakage current Vin Overdriven inverter 14

Vth Control with Multiple Vdd’s (TCMS) Using only two Vdd’s saves leakage only in P-type FinFETs, but not in N-type FinFETs Solution Use a negative ground voltage (VHss) to symmetrically save leakage in N-type FinFETs VddH VddL Symmetric threshold control for P and N VddH 1.08V VddL 1.0V VssH -0.08V VssL 0.0V TCMS buffer VssH VssL 15

Exploratory Buffer Design lopt S1 S2 VHdd VHss VLss VLdd i i’ Size of high-Vdd inverters kept small to minimize leakage in them Wire capacitances not driven by high-Vdd inverters Output inverter in each buffer overdriven and its size (and switched capacitance) can be reduced 16

Power Savings Power component Savings Dynamic power -29.8% Leakage power 57.9% Total power 50.4% Benchmarks are nets extracted from real layouts and scaled to 32nm http://dropzone.tamu.edu/~zhouli/GSRC/fast_buffer_insertion.html 17

Fin-count Savings Transistor area is measured as the total number of fins required by all buffers TCMS can save 9% in transistor area 18

TCMS Extension Delay-minimized netlist Power-optimized netlist Power : 283.6uW Area: 538 fins Power-optimized netlist Power : 149.9uW Area: 216 fins 19

Power Reduction (ISCAS’85 Benchmarks)

Power-minimized vs Delay-minimized Netlists at 130% ATC TCMS TCMS (Single-Vth Dual-Vdd % reduction in dynamic power 53.3 49.8 51.4 % reduction in leakage power 95.8 95.7 % reduction in total power 67.6 65.3 66.3 Fin-count 65.2 59.5 61.6

Talk Outline Background Low Power FinFET Circuits Architectural Impact Unusual Logic Styles Unusual Dual-Vdd/Dual-Vth Circuits Architectural Impact Other Ongoing Work Conclusions 22

Orion-FinFET Extends ORION for FinFET-based power simulation for interconnection networks FinFET power libraries for various temperatures and technologies nodes Power breakdown of interconnection networks for different FinFET modes Power comparison for different FinFET modes under different traffic patterns

Router Microarchitecture & Pipeline Stages

Power Simulation Flow

Power Breakdown for SG/LP Modes 4X4 mesh network: 5 ports/router, 48-flit buffer/port Flit width = 128 bits Clock frequency = 1GHz Router power breakdown Network power breakdown

Bulk CMOS vs. LP-mode FinFETs Bulk CMOS simulation: 32nm predictive technology model Leakage power of bulk CMOS network 2.68X as compared to an LP-mode FinFET network

Router Leakage Power vs. Temp. Leakage power of SG-mode router grows much faster with temp. than for LP-mode Leakage power ratio at 105oC: 7:1

Talk Outline Background Low Power FinFET Circuits Architectural Impact Unusual Logic Styles Unusual Dual-Vdd/Dual-Vth Circuits Architectural Impact Other ongoing work Conclusions 29

FinFET SRAM and Embedded DRAM Design FinE: Two-tier FinFET simulation framework for FinFET circuit design space exploration: Sentaurus TCAD+UFDG SPICE model Quasi Monte-Carlo simulation for process variation analysis Thermal analysis using ThermalScope Yield estimation Variation-tolerant ultra low-leakage FinFET SRAMs at lower technology nodes Gated-diode FinFET embedded DRAMs 30

Extension of CACTI for FinFETs Selection of any of the FinFET SRAM and embedded DRAM cells Use of any of the FinFET operating modes Scaling of FinFET designs from 32nm to 22nm, 16nm and 10nm technology nodes Accurately modeling the behavior of a wide range of cache configurations 31

FPGA vs. ASICs Distributed non-volatile nano RAMs: main storage for reconfiguration bits Fine-grain reconfiguration (even cycle-by-cycle) and logic folding More than an order of magnitude increase in logic density and area-delay product Competitive performance and moderate power consumption Non-volatility: useful in low power & secure processing NanoMap to map application to NATURE Significant area-delay trade-off flexibility CMOS fabrication compatible Nano RAM on-chip storage Run-time reconfiguration NATURE Temporal logic folding Design flexibility Logic density

Conclusions FinFETs a necessary semiconductor evolution step because of bulk CMOS scaling problems beyond 32nm Use of the FinFET back gate leads to very interesting design opportunities Rich diversity of design styles, made possible by independent control of FinFET gates, can be used effectively to reduce total active power consumption TCMS able to reduce both delay and subthreshold leakage current in a logic circuit simultaneously Time has arrived to start exploring the architectural trade-offs made possible by switch to FinFETs