1. Low-power FinFET Circuit Design
Niraj K. Jha
Dept. of Electrical Engineering
Princeton University
Joint work with: Anish Muttreja and Prateek Mishra

2. Talk Outline Background Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdd’s (TCMS)
Extension of TCMS to Logic Circuits
Conclusions

3. Why Double-gate Transistors ?
Feature size
32 nm
10 nm
Bulk CMOS
DG-FETs
Gap
Non-Si nano devices
DG-FETs can be used to fill this gap
DG-FETs are extensions of CMOS
Manufacturing processes similar to CMOS
Key limitations of CMOS scaling addressed through
Better control of channel from transistor gates
Reduced short-channel effects
Better Ion/Ioff
Improved sub-threshold slope
No discrete dopant fluctuations

4. Different Types of DG-FETs
Source: ( Hollis, Boston University)

5. What are FinFETs? Fin-type DG-FET
A FinFET is like a FET, but the channel has been “turned on its edge” and made to stand up
Si Fin

6. FinFET 3-D Structure
Earliest FinFET processes: both gates inherently connected
Source: (Ananthan, 2004)

7. Independent-gate FinFETs
Back Gate
Oxide insulation
Both the gates of a FET can be independently controlled
Independent control
Requires an extra process step
Leads to a number of interesting analog and digital circuit structures

8. FinFET Width Quantization
Electrical width of a FinFET with n fins: W = 2*n*h
Channel width in a FinFET is quantized
Width quantization is a design challenge if fine control of transistor drive strength is needed
E.g., in ensuring stability of memory cells
FinFET structure
Ananthan, ISQED’05

9. Talk Outline Background Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdd’s (TCMS)
Extension of TCMS to Logic Circuits
Conclusions

10. Motivation: Power Consumption
Traditional view of CMOS power consumption
Active mode: Dynamic power (switching + short circuit + glitching)
Standby mode: Leakage power
Problem: rising active leakage
40% of total active mode power consumption (70nm bulk CMOS) †
†J. Kao, S. Narendra and A. Chandrakasan, “Subthreshold leakage modeling and reduction techniques,” in Proc. ICCAD, 2002.

11. Low-power Design Techniques
Standby mode
Examples: Sleep transistor insertion, clock gating, minimum leakage vector application
Interfere with (disable/slow) circuit operation
Do not address active mode leakage
Active mode: Circuit optimization
Examples: Gate sizing, Multiple Vdd/Vth
Respect circuit operations and timing constraints
Can be used to reduce active mode leakage
What opportunities do FinFETs provide us ?

12. Talk Outline Background Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdd’s (TCMS)
Extension of TCMS to Logic Circuits
Conclusions

13. FinFETs for Low-power Design
FinFET device characteristics can be leveraged for low-power design
Static threshold voltage control through back-gate bias
Area-efficient design through merging of parallel transistors
Independent control of FinFET gates also provides novel circuit design opportunities

14. Logic Styles: NAND Gates
SG-mode NAND
IG-mode NAND
IG-mode
pull up
pull up bias voltage
LP-mode NAND
IG/LP-mode NAND
LP-mode
pull down
pull down bias voltage

15. Comparing Logic Styles
Design Mode
Advantages
Disadvantages SG
Fastest under all load conditions
High leakage† (1μA) LP
Very low leakage (85nA), low switched capacitance
Slowest, especially under load. Area overhead (routing) IG
Low area and switched capacitance
Unmatched pull-up and pull-down delays.
High leakage (772nA)
IG/LP
Low leakage (337nA), area and switched capacitance
Almost as slow as LP mode
†Average leakage current for two-input NAND gate (Vdd = 1.0V)

16. FinFET Characteristics
Simulated Id Vs. Vgs
characteristics for FinFETs at varying back-gate reverse biases
LP-mode leakage is 10 times lower than SG-mode
LP-mode delay (∞ 1/Ion) is twice that of SG-mode
IG-mode Ion is not much better than LP-mode
Ioff is a strong function of back-gate reverse bias but Ion is not

17. Back-gate Bias Voltage
Value of back-gate bias voltage affects speed and leakage
Heuristic: compare LP-mode inverter delay and leakage
Bias values
Pull-down= -0.2 V
Pull-up = Vdd + .18V (1.18V). Adjusted to match delays
Delay and leakage power variation
with back-gate bias voltage for
LP-mode FinFET inverter

18. Technical Challenges in FinFET-based Circuit Design
Wide variety of logic styles possible (can be used simultaneously)
No comprehensive circuit-level comparisons available
Circuit synthesis challenges
Industry-standard standard cell-based synthesis is often suboptimal
FinFET width quantization is based on solving a convex integer formulation†
Complex
Does not handle all logic styles
†B. Swahn and S. Hassoun, ``Gate sizing: FinFETs vs 32nm bulk MOSFETs,” in Proc. DAC, 2006

19. Our Approach Construct FinFET-based Synopsys technology libraries
Extend linear programming based cell selection† for FinFETs
Use optimized netlists to compare logic styles at a range of delay constraints
32 nm PTM
FinFET models
Delay/power
characterization in
SPICE LP
IG/LP IG SG
Synopsys libraries
inFET models
32nm PTM
Logic gate
designs
Benchmark
Minimum-delay
synthesis in
Design Compiler
SG-mode
netlist
Power-optimized mixed-mode netlists
SG+
IG/LP
SG+IG
SG+LP
Linear programming
based cell selection
†D. Chinnery and K. Keutzer, “Linear programming for sizing, Vdd and Vt assignment,” in Proc. ISLPED, 2005.

20. Power Consumption of Optimized Circuits
Estimated total power consumption for ISCAS’85 benchmarks
Vdd = 1.0V, α = 0.1, 32nm FinFETs
Available modes
Leakage power savings
120% a.t. (68.5%)
200% a.t. (80.3%)
Total power savings
110% arrival time (a.t.) (34%)
200% a.t. ( 47.5%)

21. Optimized Circuit Constitution
Fraction of cells in different FinFET modes in power-optimized FinFET circuits
Available modes
SG-mode cells are largely replaced by cells in other modes
SG-mode cells only needed on critical paths
Utilization of IG/LP-mode cells is higher than IG cells
Result of unmatched delay and higher leakage of IG-mode cells compared to IG/LP-mode cells

22. Area Requirements for Optimized Circuits
+18.8%
+18.0%

23. Talk Outline Background Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdd’s (TCMS)
Extension of TCMS to Logic Circuits
Conclusions

24. Future of Interconnect Power
Interconnect power dissipation is projected to dominate both dynamic and static power
Assorted projections from literature-
Interconnect switched capacitance may be 65-80% of total on-chip switched capacitance at the 32nm node [1]
In power-optimized buffered interconnects at 50nm, leakage power consumption may be > 80% of total interconnect power [2]
[1] N. Magen et al., Interconnect Power Dissipation in a Microprocessor, System-level Interconnect Prediction, 2004
[2] K. Banerjee and A. Mehrotra, Power Dissipation Issues in Interconnect Performance Optimization for Sub-180 nm Designs, Symp. VLSI Circuits, 2002 24

25. Gate Coupling
Linear relationship between threshold voltage and back-gate voltage in the subthreshold region
Stronger than the square root relationship between body bias and threshold effect observed in bulk-CMOS 25

26. Dual-Vdd FinFET Circuits
Conventional low-
power principle:
1.0V Vdd for critical logic, 0.7V for off-critical paths
Our proposal: overdriven gates
Overdriven FinFET gates leak a lot less!
Reverse bias
Vgs=+0.08V
Higher Vth
1.08V 1V
Leakage current
Vin
Overdriven inverter

27. threshold control for P and N
TCMS
Using only two Vdd’s saves leakage only in P-type FinFETs, but not in N-type FinFETs
Solution
Use a negative ground voltage (VHss) to symmetrically save leakage in N-type FinFETs
VddH > VddL
VssH < VssL
VddH
VddL
Symmetric
threshold control for P and N
VddH
1.08V
VddL
1.0V
VssH
-0.08V
VssL
0.0V
VssH
VssL
TCMS buffer

28. Voltage Level Conversion
Static leakage in multiple-Vdd designs
Low-Vdd inputs must be up-converted to high-Vdd before being used to drive high-Vdd inverters to avoid static leakage
Dedicated level converters inserted between buffers must be sized prohibitively large in order to avoid delay penalties [1].
Level conversion is built into high-Vdd inverters through the use of high-Vt FinFETs
[1]. K. H. Tam and L. He, Power-optimal Dual-Vdd Buffered Tree Considering Buffer Stations and Blockages, DAC 2005 28

29. Exploratory Buffer Design
Size of high-Vdd inverters kept small to minimize leakage in them
Wire capacitances not driven by high-Vdd inverters
Output inverter in each buffer overdriven and its size (and switched capacitance) can be reduced
High- and low-Vdd inverters alternate, providing maximum opportunities for power savings 29

30. Link Design
SPICE simulation to minimize power consumption in TCMS link while remaining within 1% of the delay of the single Vdd link
Parameter
Single Vdd
TCMS
Change
Link length(lopt)
0.199mm
Inverter widths
(s1, s2)
42, 84
30, 50
-36.5%
Delay (ps)
12.19
12.27
0.65%
Power (μW)
1080
647
-40% 30

31. Interconnect Synthesis
Problem: Insert buffers on a given wiring tree to meet a given delay bound while minimizing total power consumption
Two types of buffers considered
TCMS buffers
Dual-Vdd buffering scheme†
A van Ginneken-style dynamic programming buffer insertion algorithm developed
†Y. Hu et al, Fast Dual-Vdd Buffering based on Interconnect Prediction
and Sampling, SLIP 2007 31

32. Power Savings
Power component
Savings
Dynamic power
-29.8%
Leakage power
57.9%
Total power
50.4%
Benchmarks are nets extracted from real layouts and scaled to 32nm 32

33. Fin-count Savings
Transistor area is measured as the total number of fins required by all buffers
TCMS can save 9% in transistor area 33

34. Talk Outline Background Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdd’s (TCMS)
Extension of TCMS to Logic Circuits
Conclusions

35. Traditional Dual-Vdd Dual-Vth Schemes
Logic gates on the critical path driven with high-Vdd and low-Vth; those on the non-critical path with low-Vdd and high-Vth
Exponential increase in leakage current
Overhead of level converter delay and power

36. TCMS Extension =1.08V = -0.08V =1.0V =Gnd Overdriven gates are faster
Overdriven gates leak less

37. Logic Library Design FinFETs connected to input-a cannot
Embedded in a large circuit
FinFETs connected to input-a cannot
exploit TCMS
FinFETs connected to input-b have high
static leakage
FinFETs connected to input-a
follow TCMS
FinFETs connected to input-b
cannot exploit TCMS

38. Logic Library Design (Contd.)
Level conversion may be used to restore signal to VddH
Level converters not an attractive option in TCMS
Level conversion can be built into logic gates through the use of
high-Vth FinFET

39. Logic Library Design (Contd.)
Two-input NAND gate of a given size has five design variables:
Supply voltage
Gate input voltage for input-a
Gate input voltage for input-b
Vth for FinFETs connected to input-a
Vth for FinFETs connected to input-b

40. Logic Library Design (Contd.)
32 NAND gate modes possible
Certain combinations not allowed (High-Vdd gate with low-Vth transistors
cannot have high input voltage swings)
25 NAND and NOR gate modes
7 INV gate modes
For each NAND, NOR and inverter mode: X1, X2, X4, X8 and X16 sizes

41. Optimization Flow Combinational gate level Verilog netlist
Shorted-gate library
Delay-minimized netlist from Design Compiler
TCMS
library
Phase I: Divide into alternate levels of high (odd) and low (even) Vdd gates
Phase II: Linear programming
formulation
T≤Tmax no
yes
yes
P   no
Optimized netlist

42. Experimental Setup Switching activity at primary inputs set to 0.1
Temperature: 75oC
Technology node: 32nm
Nominal-Vdd: (1.0V,0V), High-Vdd: (1.08V,-0.08V)
Nominal-Vth: (0.29V,-0.25V),
High-Vth: (0.45V,-0.40V)
Cell libraries characterized using HSPICE based on PTM1 in Synopsys-compatible format
Interconnect delay and load modeled
5 sizes for logic gates: X1, X2, X4, X8 and X16
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43. Applying Methodology to c17
Delay-minimized netlist
Power : 283.6uW (leakage power:
10.3uW, dynamic power: 273.3uW)
Area: 538 fins
Power-optimized netlist
Power : 149.9uW (leakage power: 2.0uW, dynamic power: 147.9uW)
Area: 216 fins

44. Multi-Vdd Multi-Vth (1.3Tmin)

45. Multi-Vdd Single-Vth (1.3Tmin)

46. Fin-count Savings (1.3Tmin)

47. Conclusions
FinFETs are a necessary step in the evolution of semiconductors because bulk CMOS has difficulties in scaling beyond 32 nm
Use of the back gate leads to very interesting design opportunities
Rich diversity of design styles, made possible by independent control of FinFET gates, can be used effectively to reduce total active power consumption
IG/LP mode circuits provide an encouraging tradeoff between power and area
TCMS able to reduce both delay and subthreshold leakage current in a logic circuit simultaneously