© 2015 Synopsys, Inc. All rights reserved.1 Timing Analysis in a Mixed Signal World TAU Workshop Panel Session Jim Sproch March 12, 2015

© 2015 Synopsys, Inc. All rights reserved.2 Are Existing Delay Models Useful for Mixed Signal Timing Analysis? Mixed signal designs comprise a mix of digital, analog, and analog-ish circuits Partitioning ideally puts model boundaries at a digital interface Existing delay modeling syntax and semantics were designed for digital circuit applications –Some properties are transferrable to mixed signal –Capacitance, pulse noise, voltage swing, current source/sink –Some analog mixed signal properties are absent –Gain, bandpass, analog noise, frequency response, jitter, phase error, acquisition and tracking range

© 2015 Synopsys, Inc. All rights reserved.3 Abstract Models for Mixed Signal Encapsulation of function and key interface parameters –Functionality, timing, noise, variation (LVF), drive strength –Electromigration (EM), pin load capacitance, static/dynamic power Liberty™ open-source standard for library models –Non-linear table format (NLDM) –Current-source format (CCS, ECSM) –Diverse industry participation via LTAB Complementary interoperability with IEEE-1801 (UPF, CPF) power intent standard

© 2015 Synopsys, Inc. All rights reserved.4 Do Models Work for Mixed Signal? Model interfaces are a challenge for even digital circuits –Non-linear waveform effects –Simultaneous, or near-simultaneous switching –Complex input impedance Models do add value for mixed signal designs –Encapsulation in a black box model for hierarchical verification –Pin-to-pin arcs to support timing propagation Technical challenges –External cross-talk –Impedance shielding –Composite and macro modeling

© 2015 Synopsys, Inc. All rights reserved.5 Transistor-Level Static Timing Analysis STA for custom digital and interface circuits –Hierarchical SPICE netlist and transistor model card input –Exhaustive, vector-free verification of digital timing constraints –Support for digital circuits in an analog context, e.g. DCVSL, SerDes –Support for memories and particular analog-ish circuit topologies Timing constraint coverage –Complete set of combinational and sequential checks –Setup, hold, recovery, removal, min pulse width –Mixed-signal checks include –Differential clock and data signals, sense amp enable, synchronizers, precharge, level shifters, contention resolution –Ultra-fast custom digital circuits: Verilog-A monitor in every DFF instance –Characterization to encapsulate in a Liberty extracted timing model Technical challenges –Full analog circuits, PLL, ADC, DAC, switch-cap, LRC LVsig HVsig VddL VddH

© 2015 Synopsys, Inc. All rights reserved.6 Co-Simulation for Mixed Signal Designs Combine SPICE with a logic simulator Functional, timing, and power-up simulation –High throughput –Excellent accuracy Let SPICE do what SPICE does best, and use fast logic simulation to handle RTL and gate-level circuits –Various SPICE engines, + –SystemVerilog, Verilog, Verilog-A, Verilog-AMS, or VHDL Direct kernel integration of SPICE and logic simulation –Single process, single executable –Multi-level verification Use abstracted models for system-level validation

© 2015 Synopsys, Inc. All rights reserved.7 Bottom Line Mixed signal modeling and timing analysis CAN be done –Enables ultra-fast, ultra-small, ultra-low-power designs –Valuable verification technique to ensure working first silicon Technical challenges –MS circuit timing analysis is not necessarily easy or exhaustive –Labor and compute resources can be expensive –Costs may really explode with increasing number of corners Continuing progress –Modeling interface improvements –Expanding analysis support for analog-ish circuits

© 2015 Synopsys, Inc. All rights reserved.8 Thank You