1. Created by Luis Chioye Presented by Cynthia Sosa
Understanding the SAR Reference Input Model TIPL 4504 TI Precision Labs – ADCs
Created by Luis Chioye
Presented by Cynthia Sosa
Hello, and welcome to the TI Precision Lab series covering the SAR ADCs reference input. In the last section we looked in detail at the operation of the CDAC. In this section we will develop a SPICE model based on the CDAC operation. Let’s take a closer look at the agenda for this session.

2. Agenda Reference Performance Specifications:
Initial Accuracy, Drift, Long Term Drift, and Noise
Overview of SAR REF Drive Topologies:
Reference standalone VS Buffered Reference
SAR ADCs with Internal Reference Buffer
SAR REF Input Overview: The Capacitive DAC (CDAC)
Build TINA REF Input Model for a SAR:
Discrete Charge Model
TI Device Specific Model
SAR REF Drive Circuit Design:
Reference Bypass Capacitor
Reference Buffer Stability and Compensation
Here we have the agenda for the entire reference series. In this section we will develop a custom SAR ADC reference input SPICE model based on datasheet parameters. This particular model is called the “Discrete Charge model” and is based on the switching capacitive load of the SAR ADC at the reference input. The SPICE model can be used to verify the settling performance on the voltage reference input so that we can be confidant that ADC performance is not limited by the reference design. The Let’s get started…

3. Important Datasheet Parameters
Example: ADS B, 1-MSPS, Fully-Differential Input ADC
Sampling Rate = 1-MSPS
Throughput Period: tcycle=1µs
Conversion Time: tconv=710ns (max)
RSH
Input Equivalent Circuit: RSH / CSH
CSH
In this presentation we will use the ADS bit 1Msps converter as our example. The equivalent input circuit shown here is taken from the data sheet. Most ADC data sheets have a similar equivalent input circuit schematic. This is a good starting point for the SAR reference input model development. Remember, in the last section we learned that the sample and hold capacitor is actually part of the CDAC, so we will use this information to develop the reference input SPICE model. If this circuit is not provided, the sample-and-hold capacitance, Csh, is normally given in the data sheet table. The sample and hold resistance, Rsh, is typically shown in the equivalent input circuit schematic as well. If not available, Rsh can be estimated to be in the range of 50Ω to 100Ω.

4. Important Datasheet Parameters
Example: ADS B, 1-MSPS, Fully-Differential Input ADC
VREF = 5V
Fully-Differential Input ADC
Full-scale Range: ±VREF = ±5V = 10V
ADC Resolution / Least Significant Bit (LSB):
The reference voltage must remain stable and settled within the resolution of the SAR ADC. Any error in the reference voltage will directly translate into an error in output code. When performing simulations, the settling errors of the reference voltage are compared against the Least Significant Bit (LSB) value. Ideally, you want the reference settling error due to reference input current transients to be less than one half of an LSB.
This slide shows how to calculate the LSB resolution of the SAR ADC. In this example, the fully-differential SAR has a full-scale range of ±VREF. The reference voltage is 5V and therefore the full-scale range is ±5V or 10V. Since this ADC has 18-Bit resolution, the LSB value can be calculated as 38.14uV by dividing the full scale range by 2 to the 18th power.

5. Important Datasheet Parameters
Example: ADS B, 1-MSPS, Fully-Differential Input ADC
“Average” Reference Input Current:
Not a DC Current, combination of large fast current transients !!
‘Average’ Reference Input Current
at full throughput
Another useful datasheet parameter is the average reference input current. This parameter is typically specified at full-throughput of the device.
It is important to remember that this parameter is not a DC or static current, but rather a dynamic current. This current consumption represents the average of fast dynamic transient current spikes resulting from the switching of the binary weighted capacitive load at the reference input.
The average reference input current consumption is useful to verify the accuracy of the reference input simulation model. We will discuss this in more detail in the upcoming slides.

6. Estimate REFIN Capacitive Load:
Simplify/Redraw as SE circuit
NOTE: REFIN Cmsb not always ¼ Csh; depends on device Architecture!!
This is a first order estimate.
In this slide we show how to use the input equivalent circuit from the data sheet to develop the “Discrete Charge SPICE model”. During the development of this model, we will step through the acquisition and conversion phase to develop a simplified circuit that simulates the ADC reference input capacitive loading. The last video covering the operation of the CDAC is helpful in understanding this model development. Let’s start the model development by looking at the acquisition phase. During the acquisition phase, the sample-and-hold capacitor connects to the external circuit. In this example, the differential signal connects to the SAR ADC differential sample-and-hold structure.
For the purposes of the reference model, we don’t really need to model the differential input, so the circuit can be redrawn as a single-ended circuit, with only one Csh capacitor.
Remember, the sample and hold capacitor, Csh, is actually a binary weighted array of capacitors inside of the CDAC. In this step, we split the array into it’s most significant bit (MSB) capacitor and the rest of the array. The MSB capacitor is equal to half of Csh, or 27.5pF in this example, and the rest of the array is equal to the other half.
When the acquisition phase ends, the acquisition switch (SW_acq) disconnects from the external circuit and connects to ground. The hold switch connects Csh to the internal comparator. Csh holds the sampled voltage (VIN), where the comparator sees a negative voltage (-VIN)
This last section is really the most important in the development of the model. During the Most Significant Bit decision, the MSB capacitor connects to the reference input (VREF) and the remainder of the binary weighted capacitor (Crest) connects to GND. Thus, Vref is connected across a series circuit of two 27.5pF capacitors. Remember, that series capacitors add like resistors in parallel, so the total load capacitance is 27.5pF / 2 or Csh/4.
Therefore, the worst case capacitive switching load to the reference input occurs during the MSB bit decisions, where the reference input sees as effective load of Csh/4. However, it is important to notice that the worst case load is not always Csh/4, but it can be dependent on the device architecture. This model will approximate the reference loading by repeating the MSB decision multiple times. This will create a “worst case” type model. Ultimately, creating a model that fully considered all of the different capacitors in the array would be very complex and would potentially have convergence issues. This simplified worst case model will work well for confirming the reference settling, and the SPICE simulation will converge much more quickly than a more complex model.

7. Conversion Period and Conversion Clock Timing
ADS8881 uses an internal conversion clock (CCLK)
Datasheet Specifies tconv min
Estimate internal Conversion Clock period
This slide shows the timing diagram during the conversion period of the ADC. We will use the conversion period to estimate the internal conversion clock frequency based on the resolution of the ADC.
To estimate the conversion clock frequency, we use the minimum conversion time specification. The minimum conversion time is used, because it defines the fastest conversion clock which will be the worst case for reference settling. For this example, the conversion time is 500ns and we divide by 18 clock pulses because the ADS8881 is an 18 bit converter. This gives 28ns between conversion steps, so we will connect the reference capacitive load every 28ns during the conversion phase.

8. TINA SPICE Equivalent Model
tCNTL =40ns*8=320ns (mask)
4-8 transients (1*CSH, 2*CSH)
(Only 8 transients per conv)
Conversion Clock (CCLK)
tcclk =30ns (33.3MHz)
Resets
CREF to 0V
RSH
CLOAD = 1/4 CSH= 13.75pF
This is the schematic of the ADC Reference input model and reference driver circuit for our design. The Discrete Charge Model is a conservative capacitive load model that allow us to approximate the reference input load.
Let’s do a brief high level overview. On the left hand side is the REF6050 voltage reference, and the required 47uF reference input bypass capacitor. Notice, the REF6050 incorporates a high speed buffer that allows the device to drive directly the reference input of the SAR ADC without an external buffer.
The previous analysis showed that the worst case capacitive load seen by the reference input is Csh/4. This is the loading that occurs during the MSB bit decisions, which is 13.75pF for this example.
Rsh represents the internal switch resistance, typically shown in the datasheet equivalent input sample-and-hold schematic. If not available, Rsh is typically in the range of 50Ω to 100Ω.
SW_BIT controls the switching of the CDAC capacitor. The reference is sampled many times for every single conversion, at the conversion clock frequency. In this example, the conversion clock period is estimated at 30ns.
SW_CNTL masks the number of times the reference is sampled every conversion cycle. In this approximate model, the reference is sampled 8 times per conversion, where the reference input sees a worst case capacitive load CREF=13.75pF eight times per conversion.
SW_BIT_R resets the voltage across CREF to zero volts every conversion clock cycle.
Again, this is a simplified conservative model, approximating the reference input load. In the real SAR ADC, the reference input is sampled several times per conversion cycle, the reference is sampled every binary weighted bit decision. Also, in the real device, the load is a binary weighted capacitor, where largest capacitive load occurs during the MSB decision and the binary weighted capacitor decreases size for the least significant bit decisions. Nevertheless, this simplified model is works well for verification of the reference settling circuit as it models the worst case transient.

9. TINA SPICE Equivalent Model
This Slide shows the waveforms of the switch signals. The switches are closed when the voltage is ‘1’ and open when the voltage is ‘0’.
SW_BIT controls the switching of the CDAC capacitor. The reference is sampled several times during the conversion period, for each ADC bit decision, at the conversion clock frequency. In this example, the conversion clock period is estimated at 30ns.
SW_CNTL masks the number of times the reference is sampled on each conversion cycle. In this approximate model, the reference is sampled 8 times per conversion, where the reference input sees a worst case capacitive load CREF=13.75pF eight times per conversion.
SW_BIT_R resets to 0V the voltage stored on the CREF capacitor every conversion clock cycle. Thus, CREF will be fully discharged before the next time SW_BIT is closed.

10. Thanks for your time!
That concludes this video. In the next video we will go over the details of how to configure the different circuit elements in the model. Thank you for watching! Please try the quiz to check your understanding of this video’s content.

11. This slide should be leveraged for external recordings
This slide should be leveraged for external recordings. Leave on screen for 5 seconds.