1. PUT JOSH WEB- STREAM HERE

2. 4/30/2010 Iowa State University EE492 – Senior Design II

3.  International collaboration  Product conceptualization & specification in addition to design  Integrated circuit (IC) rather than system design  Research-orientated objectives

4.  Design a test chip to support ISU research on electromigration & IC reliability  The chip must include test structures composed of actual metal interconnects in a modern silicon process  Must be capable of interfacing with a controller to allow electrothermal conditions in the chip to be varied and monitored.

5.  Electromigration – a complex physical phenomena that causes mechanical stress in metal interconnects  Important failure mechanism in ICs  Strong, non-linear dependence on current-density and temperature  Need models for electromigration that predict reliability under practical conditions Electromigration in progress!

6.  Subject interconnects to variable electrothermal stresses  Measure time-to-failure of many samples  Analyze statistics, develop models, fit data, etc.  Use accelerated lifetime technique  Very high temperatures and current densities!

7.  Proposed IC contains 8 identical metal test structures  Current-steering Digital-to- Analog Converter provides 0-25mA to test structure  On-die analog temperature sensing circuits  Open-circuit detection  Control logic with serial interface  Process technology: 0.18 µm standard CMOS

9.  Single-layer metal interconnect with serpentine pattern Metal layerM1 Width0.23 µm Equivalent lengthUp to 11.5 mm Thickness210 nm MaterialCu

10.  Corners reinforced to mitigate current crowding

11.  Current range of 0 to 25 mA  7 bit resolution  LSB Current – 200 µA  Current-Steering Architecture  Binary-weighted sources  Constant power  Open Circuit Detection  Two inverters on the output DAC 0010110

13.  Compact, CMOS-based sensor design  5 sensor distributed throughout the floor plan

14.  Serial interface  Simple protocol  Low pin-count

15.  Needed standard cell library for synthesis  Free, scalable library did not meet design rules of our process  Extensive work to customize, re-verify standard cells

16.  Master current switch  Reference-distribution network

17.  Floorplan symmetry to prevent uncontrolled experimental variables  Significant redundancy and reinforcement of non-test blocks for reliability  Final design is 860 µm x 860 µm

19.  Analog verification: relevant performance parameters for each block tested over full PVT range with 500-run statistical simulations  Digital verification: functional simulations, timing analysis  System-level, mixed-signal verification: several long transient simulations covering typical operation sequence

20. #1 VDD rises #2 Reference current starts #3 written to address reg. #4 written to address reg. #5 master current switch enabled #6 test current settles at predicted value

22.  DAC  Temperature sensor  Top-level functional