1 Lecture 28 Timing Analysis

2 Overview °Circuits do not respond instantaneously to input changes °Predictable delay in transferring inputs to outputs Propagation delay °Sequential circuits require a periodic clock °Goal: analyze clock circuit to determine maximum clock frequency Requires analysis of paths from flip-flop outputs to flip-flop inputs °Even after inputs change, output signal of circuit maintains original output for short time

3 Understanding Sequential Circuit Timing °Two characteristics of a computer System Processor clock speed Size of its main memory Main memory size (the number of storage bits in the computer) Clock speed involves analysis of the timing parameters of combinational and sequential circuit components

4 Sequential Circuits °Sequential circuits can contain both combinational logic and edge-triggered flip flops °A clock signal determines when data is stored in flip flops °Goal: How fast can the circuit operate? Minimum clock period: T min Maximum clock frequency: f max °Maximum clock frequency is the inverse of the minimum clock period 1/T min = f max Clock Period Clock The amount of time between rising clock edges is called the clock period, T per, of the clock

5 Timing Parameters for Combinational Logic °Propagation delay (t pd ) - This value indicates the amount of time needed for a change in a logic input to result in a permanent change at an output. °Combinational logic is guaranteed not to show any further output changes in response to an input change after t pd time units have passed. °Contamination delay (t cd ) indicates the amount of time needed for a change in a logic input to result in an initial change at an output [1]. °Combinational logic is guaranteed not to show any output change in response to an input change before t cd time units have passed.

6 Timing Parameters for Combinational Logic A A

7 Combinational Logic Timing: Inverter °Combinational logic is made from electronic circuits An input change takes time to propagate to the output °The output remains unchanged for a time period equal to the contamination delay, t cd °The new output value is guaranteed to valid after a time period equal to the propagation delay, t pd or °After the propagation delay, t pd, the inverter output is stable and is guaranteed not to change again until another input change. A Y t pd t cd A change in Y is not instantaneous.

8 Combinational Logic Timing: Inverter °Combinational propagation delays are additive °Combinational propagation delay, t pd is calculated by adding the propagation delays of the circuit components along the longest path A Y t pd t cd A change in Y is not instantaneous.

9 Combinational Logic Timing: XNOR Gate °The output is guaranteed to be stable with old value until the contamination delay Unknown values shown in waveforms as Xs °The output is guaranteed to be stable with the new value after the propagation delay

10 Combinational Logic Timing: Complex Circuits °Propagation delays are additive Locate the longest combination of t pd °Contamination delays may not be additive Locate the shortest path of t cd °Find propagation and contamination delay of new, combined circuit A B C A B C Circuit X T pd = 5ns T cd = 1ns T pd = 2ns T cd = 1ns T pd = 3ns T cd = 1ns

11 Timing Parameters for Combinational Logic °Longest delay from a circuit input (w, x, y) to the output z is the sum of the component propagation delays through gates A and B, 3 ns + 2 ns = 5 ns °4 ns propagation delay path through gates C and B can be ignored in determining the overall propagation delay of the circuit since it is shorter than 5 ns

12 Timing Parameters for Combinational Logic °In contrast, the determination of the contamination delay of the combined circuit requires identifying the shortest path of contamination delays from input to output. °Contamination delay of the combined circuit is 2 ns, since the shortest sum of contamination delays from an input (y) to an output (z), is tcd(C) + tcd(B) = 1 ns + 1 ns = 2ns °this value is smaller than the contamination delay path through gates A and B (2 ns + 1ns = 3 ns)

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14 Timing Parameters for Sequential Logic °Sequential circuits, such as edge-triggered flip-flops exhibit certain timing characteristics °Unlike combinational, timing parameters for clocked devices are specified in relation to the clock input (rising edge) °Flip-Flops only change value in response to a change in the clock value, timing parameters can be specified in relation to the rising (for positive edge-triggered) or falling (for negative-edge triggered) clock edge °Propagation delay (t Clk−Q ) - indicates the amount of time needed for a change in the flip flop-clock input (e.g. rising edge) resulting in a permanent change at the flip-flop output (Q). °Contamination delay (t cd ) - indicates the amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output (Q).

15 Clocked Device: Contamination and Propagation Delay Propagation delay (t Clk−Q ) – indicates the amount of time needed for a change in the flip flop-clock input (e.g. rising edge) resulting in a permanent change at the flip-flop output (Q). Contamination delay (t cd ) – indicates the amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output (Q). Clk Q D t cd t Clk-Q

16 Clocked Device: Contamination and Propagation Delay °Setup time (t s ) - indicates the amount of time before the clock edge that data input D must be stable. Hold time (t h ) - indicates the amount of time after the clock edge that data input D must be held stable.

17 Clocked Devices: Setup and Hold Times t s t h Clk Q D °Timing parameters for clocked devices are specified in relation to the clock input (rising edge) °D input must be valid at least t s (setup time) before the rising clock edge °D input must be held steady t h (hold time) after rising clock edge °Setup and hold are input restrictions Failure to meet restrictions causes circuit to operate incorrectly

18 Clocked Devices: Setup and Hold Times t s t h Clk Q D °Timing parameters for clocked devices are specified in relation to the clock input (rising edge) °Setup (t s ) and hold times (t h ) are restrictions that a flip-flop places on combinational or sequential circuitry °The circuit must be designed so that the D flip flop input signal arrives at least ‘t s ‘ time units before the clock edge and does not change until at least ‘t h ‘ time units after the clock edge. that drives a flip-flop D input. °If either of these restrictions are violated for any of the flip- flops in the circuit, the circuit will not operate correctly °These restrictions limit the maximum clock frequency at which the circuit can operate

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20 Edge-Triggered Flip Flop Timing D CLK t s = setup time t h = hold time °The logic driving the flip flop must ensure that setup and hold are met °Timing values (t cd t pd t Clk-Q t s t h )

21 Analyzing Sequential Circuits °What is the minimum time between rising clock edges? T min = T CLK-Q (FFA) + T pd (G) + T s (FFB) °Trace propagation delays from FFA to FFB °Draw the waveforms! Z Comb. Logic T Clk-Q = 5 ns T s = 2 ns D Q D Q YX D CLK T Clk-Q = 5ns T pd = 5ns FFA FFB G F max = _______

22 Analyzing Sequential Circuits °What is the minimum clock period (T min ) of this circuit? Hint: evaluate all FF to FF paths °Maximum clock frequency is 1/T min Z Comb. Logic H T Clk-Q = 4 ns T s = 2 ns D Q D Q YX CLK T Clk-Q = 5ns T pd = 5ns FFA FFB Comb. Logic F T pd = 4ns

23 Analyzing Sequential Circuits °Path FFA to FFB T Clk-Q (FFA) + T pd (H) + T s (FFB) = 5ns + 5ns + 2ns = 12ns °Path FFB to FFB T CLK-Q (FFB) + T pd (F) + T pd (H) + T s (FFB) = 4ns + 4ns + 5ns + 2ns Z Comb. Logic H T Clk-Q = 4 ns T s = 2 ns D Q D Q YX CLK T Clk-Q = 5ns T pd = 5ns FFA FFB Comb. Logic F T pd = 4ns F max = _______

24 Analyzing Sequential Circuits: Hold Time Violation °One more issue: make sure Y remains stable for hold time (T h ) after rising clock edge °Remember: contamination delay ensures signal doesn’t change °How long before first change arrives at Y? T cd (FFA) + T cd (G) >= T h 1ns + 2ns > 2ns Z Comb. Logic T h = 2 ns D Q D Q YX D CLK T cd = 1ns T cd = 2ns FFA FFB G

25 Analyzing Sequential Circuits: Hold Time Violations °Path FFA to FFB T CD (FFA) + T CD (H) > T h (FFB) = 1 ns + 2ns > 2ns °Path FFB to FFB T CD (FFB) + T CD (F) + T Cd (H) > T h (FFB) = 1ns + 1ns + 2ns > 2ns Z Comb. Logic H T ClD = 1 ns T h = 2 ns D Q D Q YX CLK T ClD = 1ns T cd = 2ns FFA FFB Comb. Logic F T cd = 1ns All paths must satisfy requirements

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27 Determining the Max. Clock Frequency for a Sequential Circuit °Most digital circuits contain both combinational components (gates, muxes, adders, etc.) and sequential components (flip-flops). °Combinational and sequential component parameters are considered in order to determine the maximum clock frequency at which a circuit will operate and generate correct results. °Consider the flow of data in this circuit in response to a rising clock edge, starting at flip-flop A.

28 Determining the Max. Clock Frequency for a Sequential Circuit °Following the rising clock edge on Clk, a valid output appears on signal X after t Clk−Q = 10 ns. °A valid output Y appears at the output of inverter F, t pd = 5 ns after a valid X arrives at the gate. °Signal Y is clocked into flip-flop B on the next rising clock edge. This signal must arrive at least t s = 2ns before the rising clock edge.

29 Determining the Max. Clock Frequency for a Sequential Circuit Minimum clock period, Tmin of the circuit and the maximum clock frequency of the circuit is

30 Determining the Max. Clock Frequency for a Sequential Circuit Clk input is attached to both flip-flops, both will change value at the same time. On each clock edge, the same three steps starting from flip flop A are repeated. There are often millions of flip-flop to flip-flop paths that need to be considered in calculating the maximum clock frequency. Locate the longest path among all the flip-flop paths in the circuit

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32 Validating Flip-Flop Hold Time Designing a circuit for a specific maximum clock frequency is not enough to ensure that the circuit will work properly Hold time, t h must be satisfied for each flip-flop input, indicating that each D input cannot change until t h time units after the clock edge Contamination delays of combinational circuitry and flip-flops help prevent flip- flop inputs from changing instantaneously

33 Validating Flip-Flop Hold Time Hold time requirement on flip-flop B indicates that the Y input to flip-flop B should not change until at least 2 ns after the rising clock edge of Clk The earliest the signal can start to change is equal to the sum of the contamination delays of flip-flop A and inverter X t h, 2 ns, is less than t cd (A) + t cd (B), 4 ns, The hold time is satisfied and the circuit will work correctly

34 Validating Flip-Flop Hold Time Hold time requirement on flip-flop B indicates that the Y input to flip-flop B should not change until at least 2 ns after the rising clock edge of Clk Hold time requirement on flip-flop B indicats that the Y input to flip-flop B should not change until at least 2 ns after the rising clock edge of Clk

35 Sequential Circuit Timing °Sequential circuits rely on a clock signal to control the movement of system data °Given a set of combinational and sequential components and their associated timing parameters, it is possible to determine the maximum clock frequency that can be used with the circuit °This analysis includes the examination of every flip-flop to flip-flop path in the circuit °Moreover it includes both the propagation delays along the paths and the data setup time at the destination flip-flop. °Following the calculation of the maximum clock frequency, each flip-flop to flip-flop path can be examined to ensure that flip-flop hold times are satisfied.

36 Summary °Maximum clock frequency is a fundamental parameter in sequential computer systems °Possible to determined clock frequency from propagation delays and setup time °The longest path determines the clock frequenct °All flip-flop to flip-flop paths must be checked °Hold time are satisfied by examining contamination delays °The shortest contamination delay path determines if hold times are met °Check handout for more details and examples.