Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 17 - Sequential Logic Timing, Testing Spring 2007

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)2 Announcements  Reading  Book: ,  Verilog Handout: Section 5

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)3 Where We Are  Last Time:  Sequential Circuit Timing (intro)  Today:  Sequential Circuit Timing  Sequential Circuit Testing

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)4 Sequential Logic - General Structure  State changes on each clock cycle  Next state is function of current state, inputs  Some definitions  Moore machine: output function of current state only  Mealy machine: output depends on current state, inputs

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)5 Clocking Disciplines  Sequential logic must properly satisfy  Setup-time constraints  Hold-time constraints  Sequential logic must work given "non-ideal" behavior  Combinational logic propagation delays  Clock skew  A clocking discipline sets constraints to ensure proper operation

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)6 Clocking Disciplines (cont’d)  Basic rules:  Clocking rule 1: "Combinational logic gates cannot be connected in a cycle"  Clocking rule 2: "All components must have bounded delay"

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)7 Types of Clocking Disciplines FlopComb. LogicFlop TCTC clk Single-Phase Edge Triggered Latch t pw Comb. Logic t pw clk Single-Phase Level Triggered (“pulse latches”) Latch Comb Logic Latch t no Latch Comb Logic t no 11 22 Two-Phase Level Triggered

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)8 Some Timing Definitions  Propagation delay vs. contamination delay  Logic propagation delay (maximum) - t pd  Logic contamination delay (minimum) - t cd  Flip-flop/Latch Clock-to-Q propagation delay (maximum) - t pcq  Flip-flop Clock-to-Q contamination delay (minimum) - t ccq  Latch D-to-Q propagation delay (maximum) - t pdq  Latch D-to-Q contamination delay (minimum) - t cdq  Flip-Flop/Latch “Timing Window”  Setup time - t setup  Hold time - t hold Notation based on Weste & Harris Ch. 7

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)9 Timing Definitions - Comb. Logic Comb. Logic A Y A Y t cd t pd  Propagation delay vs. contamination delay  Logic propagation delay (maximum) - t pd  Logic contamination delay (minimum) - t cd

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)10 Timing Definitions - Flip-Flops clk Flop DQ D t ccq Q t setup thth t pcq  Propagation delay vs. contamination delay  Flip-flop Clock-to-Q propagation delay (maximum) - t pcq  Flip-flop Clock-to-Q contamination delay (minimum) - t ccq  Flip-Flop “Timing Window”  Setup time - t setup  Hold time - t hold

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)11 Timing Definitions - Latch clk Latch DQ D t ccq t setup thth t pcq  Propagation delay vs. contamination delay  Latch Clock-to-Q propagation delay (maximum) - t pcq  Latch Clock-to-Q contamination delay (minimum) - t ccq  Latch “Timing Window”  Setup time - t setup  Hold time - t hold Q t cdq t pdq

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)12 Single-Phase Edge-Triggered Clocking T c > t pcq + t pd + t setup t pd < T c - (t setup + t pcq ) t cd ≥ t hold - (t ccq + t cd ) FlopComb. LogicFlop TCTC clk

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)13 Single-Phase Level-Triggered Clocking T c > max(t pdq + t pd,t pcq + t pd + t setup - t pw ) t pd < T c - max(t pdq, t pcq + t setup - t pw ) t cd ≥ t hold - t ccq + t pw Latch t pw Comb. Logic t pw clk

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)14 Two-Phase Level-Triggered Clocking T c > t pdq1 + t pd1 + t pdq2 + t pd2 t cd1,t cd1 ≥ t hold - t ccq - t no Latch Comb Logic Latch t no Latch Comb Logic t no 11 22

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)15 Clock Skew in Single-Phase Clocking  Clock may not arrive at FF inputs at same time  Must account for clock skew in timing Adder Mux Combinational LogicRegister Output Register Input Clock t prop t setup T c ≥ t pcq + t pd + t setup + t skew t cd ≥ t hold - t ccq + t skew  t skew

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)16 More About Two-phase clocking  Break logic into two sections separated by latches  Use non-overlapping clocks ø1, ø2

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)17 Rules for reliable 2 phase design  Every cycle must be broken by both ø1 and ø2 latches  Latch inputs must be stable during active phase (sø1, sø2)  See Section for more details

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)18 Two-phase example - Dynamic Shift Reg.  Basic circuit - one stage  Operation - p. 271

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)19 Two-phase example - Dynamic Shift Reg.  Hierarchical Sticks Diagram - Multiple Phases  Tiling horizontally adds to length of shift register  Tiling vertically adds to width of shift register

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)20 Qualified clocks  Logical "AND" of enable signal, clock phase  Application: recirculating latch  Drawback: extra clock skew (unless generated carefully)

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)21 Clock Period concerns  clock period limited by longest delay  goal: balance delay between latches/registers  one way: restructure logic across latch boundaries - retiming longer delayshorter delay

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)22 Retiming  Key idea: “move” latch/register “before” gate  Properties:  Changes encoding of values in registers, but proper values can be reconstructed with combinational logic.  May increase number of registers required.  Must preserve number of latches around a cycle—may not be possible with reconvergent fanout.

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)23 Two-phase clock generation  It is essential that clock phases be non-overlapping  Generation circuit: Cross-coupled NOR "latch"

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)24 On-Chip Clock Generation  On-chip clock is usually faster than external clock  Clock doubler - phase-lock loop circuit frequency f n * f Phase Detector filter VCO divide-by-N counter off-chip clock on-chip clock

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)25 Sequential Circuit Testing  Testing Review  Apply input vectors  Compare output vectors to “known correct” Device Under Test (DUT) Input Vectors: Output Vectors:

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)26 Review - Combinational Testing  Assume Single “Stuck-At” Faults  For each fault, generate input vector that  sensitizes fault  propagates fault to output if correct 1 if faulty

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)27 Sequential Circuit Testing  Same general approach as combinational testing...  Sensitize the fault  Propagate the fault  BUT, circuit node values depend on both  circuit inputs AND  present state S-A-0 S-A-1

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)28 Sequential Testing Approach  Spread testing over multiple clock cycles  Set flip-flops to proper values to sensitize fault  Set flip-flops to proper value to propagate fault  Sequential circuit testing is hard!  May not be able to sensitize all faults  May not be able to propagate all faults

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)29 Sequential Test Example  Identify a S-A-1fault on node N1  Recall testing steps  Sensitize fault  Propagate to output

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)30 Three Clock Cycles Needed  Sensitize fault  Make Q2 = 0 (D=0,  E=0 on 1st clock)  Set C=0 on 2nd clock  Propagate fault  N1 to Q1(Set B=0)  Q1 to OUT  (A=1 on 3rd clock)

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)31 Generalizing Sequential Test  "Unroll" circuit into time frames for successive states (Fig. 5-38, p. 268)  Generate test for "unrolled" circuit  Problems  Need to get circuit into known state (reset)  Some states may not be reachable  Unrolling a fault mimics multiple faults State = 00State = 01State = 11

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)32 Design for Test  Goal: make sequential test easier  General approach: provide a different way to set, read flip-flops - scan design  Scan design key ideas  Alter flip-flop / latch design to read second input during test mode  Thread second inputs into a large "shift register"  Connect test input, output, and mode control to chip pins  Use test mode to set, read flip-flops during testing

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)33 Scan Design - General Structure

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)34 Using Scan Design  Shift in to set FF values  Shift out to read FF values  Scan variations  Full scan - require scan in all flip-flops  Partial scan - require scan in some flip-flops  Boundary scan - use scan for block I/Os (often used in board-level test)

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)35 Built-In Self Test (BIST)  Goal: provide limited testing within the chip itself  Typical approach: use Linear Feedback Shift Register (LFSR)  Structure: shift register with exclusive-OR feedback  "Pseudo-random" state sequence

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)36 BIST (cont'd)  Applications of LFSRs  Generate pseudo-random test vectors for self-test  Use as signature analyzer to compress output vectors

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)37 BIST (cont'd)  Applications of LFSRs  Generate pseudo-random test vectors for self-test  Use as signature analyzer to compress output vectors LFSR Signature Analyzer Circuit Under Test

ECE 425 Spring 2007Lecture 17 - Seq. Logic (cont'd)38 Coming Up  Sequential Design in Verilog  Architecture Design  Chip-Level Design