Verilog - 1 Writing Hardware Programs in Abstract Verilog  Abstract Verilog is a language with special semantics  Allows fine-grained parallelism to be easily expressed  ~ C syntax – easy to learn  NOT C semantics!  Abstract Verilog translated into Verilog  Hides “bad” features of Verilog  Allows standard simulators and synthesis tools

Verilog - 2 Data Values  A hardware program defines a circuit module  Module structure  Declare inputs  Declare outputs  Outputs are just local values connected to the interface  Declare local values  Define behavior inputsoutputs

Verilog - 3 module and_gate (out, in1, in2); input in1, in2; output out; COMB out;// Local variable - combinational ALWAYS begin out = in1 & in2; end endmodule Module Definition  Example combinational module

Verilog - 4 module counter (clk, reset, out, tc); input clk, reset; output [7:0] count; output tc; REGISTER [7:0] count;// Register value COMB tc; ALWAYS begin if (reset) begin count <-- 0; end else begin count <-- count + 1; end tc = (count == 255); end endmodule Module Definition  Example sequential module

Verilog - 5 Verilog Module  Corresponds to a circuit component  “parameter list” is the list of external connections, aka “ports”  ports are declared “input”, “output” or “inout”  inout ports used on tri-state buses  port declarations declare the variables as wires module full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; COMB S, Cout; ALWAYS begin {Cout, S} = A + B + Cin; end endmodule module name inputs/outputs ports signal declaration

Verilog - 6 Verilog Numbers  14 - ordinary decimal number  ’s complement representation  12’b0000_0100_ binary number with 12 bits (_ is ignored)  12’h046 - hexadecimal number with 12 bits  Verilog values are unsigned by default  e.g. C[4:0] = A[3:0] + B[3:0];  if A = 0110 (6) and B = 1010(-6) C = not i.e. B is zero-padded, not sign-extended  Use the signed declaration to declare signed numbers  COMB signed [7:0] sum;  REGISTER signed [15:0] value;

Verilog - 7 Verilog Data Types and Values  Bits - value on a wire  0, 1  X - don’t care  Z - undriven, tri-state  Vectors of bits  A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0]  Treated as an unsigned integer value unless declared signed  e.g. A < 0 ??  Concatenation operator { }  e.g. sign extend  B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};  B[7:0] = {4{A[3]}, A[3:0]};  Style: Use a[7:0] = b[7:0] + c; Not: a = b + c; // need to look at declaration

Verilog - 8 Verilog Operators

Verilog - 9 Abstract Verilog Signals  COMB  Combinational signal  Assigned using the = operator  foo = bar;  REGISTER  Signal that is the output of a register  Assigned using the <-- operator  foo <-- bar;  Value is assigned at the next clock tick (rising edge)  Note redundancy – catches simple errors

Verilog - 10 COMB A = X | (Y & ~Z); COMB [3:0] B = 4'b01XX; COMB [15:0] C = 16'h00ff; use of Boolean operators (~ for bit-wise, ! for logical negation) bits can take on four values (0, 1, X, Z) variables can be n-bits wide (MSB:LSB) Abstract Verilog Combinational Assignment  Assignment is specified in signal declaration  C orresponds to a connection or a combinational circuit  No other assignment is allowed

Verilog - 11 module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; COMB Equal = (A & B) | (~A & ~B); COMB Alarger = (A & ~B); COMB Blarger = (~A & B); endmodule Comparator Example

Verilog - 12 module and_gate (out, in1, in2); inputin1, in2; outputout; COMBout; ALWAYS begin out = in1 & in2; end endmodule The ALWAYS block  Describes functionality of module  What is executed during one clock cycle  If no clock, then what happens all the time

Verilog - 13 “Complete” Combinational Assignments  COMB signals  No feedback allowed  infinite loop  e.g. i = i + 1  All COMB signals should be assigned whenever ALWAYS block executes  COMB signals are assigned to ‘X’ by default  this means synthesis is free to pick a value  block should assign a value, unless ‘X’ is OK  What happens if you forget?  You have to trust simulation to find the invalid ‘X’s  Simulation cannot cover all cases (in general)

Verilog - 14 Register Assignments  REGISTER signals  Modules with REGISTERS must have clock  Initialization can be performed if reset is an input REGISTER count = 0;// Happens whenever reset is asserted  <-- assignment happens on the next clock tick  Feedback is of course allowed  e.g. i <-- i + 1// NextValue <-- f(CurrentValue)  If a REGISTER is not assigned, it keeps its previous value  What about multiple assignments?  Only the last <-- assignment has effect i <-- i + 2; i <-- i + 1;  Adds 1 to i, not 2, not 3  Generally a BAD idea

Verilog - 15 Verilog if  Same as C if statement // Simple 4-1 mux module mux4 (sel, A, B, C, D, Y); input [1:0] sel;// 2-bit control signal input A, B, C, D; output Y; COMB Y; ALWAYS begin// Note: Y always assigned if (sel == 2’b00) Y = A; else if (sel == 2’b01) Y = B; else if (sel == 2’b10) Y = C; else if (sel == 2’b11) Y = D; end endmodule

Verilog - 16 Verilog case  Sequential execution of cases  only first case that matches is executed (no break)  default case can be used // Simple 4-1 mux module mux4 (sel, A, B, C, D, Y); input [1:0] sel;// 2-bit control signal input A, B, C, D; output Y; COMB Y; ALWAYS begin case (sel) 2’b00: Y = A; 2’b01: Y = B; 2’b10: Y = C; 2’b11: Y = D; endcase end endmodule

Verilog - 17 module reg8 (reset, clk, D, Q); inputreset, clk; input [7:0]D; output [7:0]Q; // Set Q to 0 when reset is asserted REGISTER [7:0]Q = 0; ALWAYS Q <-- D; endmodule// reg8 8-bit Register with Synchronous Reset

Verilog - 18 Simple Counter Example // 8-bit counter with clear and count enable controls module count8 (CLK, reset, cntEn, Dout); inputCLK; inputreset;// clear counter inputcntEn;// enable count output[7:0]Dout;// counter value REGISTER [7:0] Dout = 0; ALWAYS if (cntEn)Dout <-- Dout + 1; endmodule

Verilog - 19 Shift Register Example // 8-bit register can be cleared, loaded, shifted left // Retains value if no control signal is asserted module shiftReg (clk, clr, shift, ld, Din, SI, Dout); inputclk; inputclr;// clear register inputshift;// shift inputld;// load register from Din input[7:0]Din;// Data input for load inputSI;// Input bit to shift in output[7:0]Dout; REGISTER(clk)[7:0]Dout; ALWAYS begin if (clr)Dout <-- 0; else if (ld)Dout <-- Din; else if (shift)Dout <-- { Dout[6:0], SI }; end endmodule// shiftReg

Verilog - 20 Example – Breshenham’s Algorithm module breshenham (clk, reset, x1, y1, x2, y2, x, y); input clk, reset; input [7:0] x1, y1, x2, y2; output [7:0] x, y; REGISTER t = 0; REGISTER [7:0] x, y; REGSITER [7:0] dx, dy; parameter INIT=0, RUN=1, DONE=2; REGISTER [2:0] state = INIT; COMB [7:0] temp; ALWAYS begin case (state) INIT: begin x <-- x1; y <-- y1; dx <-- x2 – x1; dy = y2 – y1; t <-- 0; state <-- RUN; end RUN: begin temp = t + dy; if (temp = dx) begin y <-- y + 1; t <-- temp – dx; end else begin t <-- temp; end x <-- x + 1; if (x >= x2) state <-- DONE; end DONE: begin... end endmodule