Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Topics n High-level synthesis. n Architectures for low power. n Testability and architecture.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR High-level synthesis n Sequential operation is not the most abstract description of behavior. n We can describe behavior without assigning operations to particular clock cycles. n High-level synthesis (behavioral synthesis) transforms an unscheduled behavior into a register-transfer behavior.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Tasks in high-level synthesis n Scheduling: determines clock cycle on which each operation will occur. n Binding (allocation): chooses which function units will execute which operations.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Functional modeling code in VHDL o1 <= i1 or i2; if i3 = ‘0’ then o1 <= ‘1’; o2 <= a + b; else o1 <= ‘0’ end if; clock cycle boundary can be moved to design different register transfers

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Data dependencies n Data dependencies describe relationships between operations: –x <= a + b ; value of x depends on a, b n High-level synthesis must preserve data dependencies.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Data flow graph n Data flow graph (DFG) models data dependencies. n Does not require that operations be performed in a particular order. n Models operations in a basic block of a functional model -no conditionals. n Requires single-assignment form.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Data flow graph construction original code: x <= a + b; y <= a * c; z <= x + d; x <= y - d; x <= x + c; single-assignment form: x1 <= a + b; y <= a * c; z <= x1 + d; x2 <= y - d; x3 <= x2 + c;

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Data flow graph construction, cont’d Data flow forms directed acyclic graph (DAG):

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Goals of scheduling and allocation n Preserve behavior - at end of execution, should have received all outputs, be in proper state (ignoring exact times of events). n Utilize hardware efficiently. n Obtain acceptable performance.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Data flow to data path-controller One feasible schedule for last DFG:

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Binding values to registers registers fall on clock cycle boundaries

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Choosing function units muxes allow function units to be shared for several operations

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Building the sequencer sequencer requires three states, even with no conditionals

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Choices during high-level synthesis n Scheduling determines number of clock cycles required; binding determines area, cycle time. n Area tradeoffs must consider shared function units vs. multiplexers, control. n Delay tradeoffs must consider cycle time vs. number of cycles.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Finding schedules n Two simple schedules: –As-soon-as-possible (ASAP) schedule puts every operation as early in time as possible. –As-late-as-possible (ALAP) schedule puts every operation as late in schedule as possible. n Many schedules exist between ALAP and ASAP extremes.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR ASAP and ALAP schedules ASAP ALAP

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Critical path of schedule Longest path through data flow determines minimum schedule length:

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Operator chaining n May execute several operations in sequence in one cycle - operator chaining. n Delay through function units may not be additive, such as through several adders.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Control implementation n Clock cycles are also known as control steps. n Longer schedule means more states in controller. n Cost of controller may be hard to judge from casual inspection of state transition graph.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Controllers and scheduling functional model: x <= a + b; y <= c + d; one state two states

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Distributed control one centralized controller two distributed controllers

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Synchronized communication between FSMs To pass values between two machines, must schedule output of one machine to coincide with input expected by the other:

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Hardwired vs. microcoded control n Hardwired control has a state register and “random logic.” n A microcoded machine has a state register which points into a microcode memory. n Styles are equivalent; choice depends on implementation considerations.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Data path-controller delay Watch out for long delay paths created by combination of data path and controller:

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Architectures for low power n Two important methods: –architecture-driven voltage scaling –power-down modes

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Architecture-driven voltage scaling n Add extra logic to increase parallelism so that system can run at lower rate. n Power improvement for n parallel units over Vref: –P n (n) = [1 + C i (n)/nC ref + C x (n)/C ref ](V/V ref )

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Power-down modes n CMOS doesn consume power when not transitioning. Many systems can incorporate power-down modes: –condition the clock on power-down mode; –add state to control for power-down mode; –modify the control logic to ensure that power- down/power-up don corrupt control state.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Architecture testing n Want to make system as testable as possible with minimum cost in hardware, testing time. n Can use knowledge of architecture to help choose testability points. n May want to modify architecture to improve testability.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Some scan latches are more useful than others n Acyclic register-transfer graphs are easy to test. n Register-transfers with feedback are harder to test - state becomes contaminated during test. n When choosing partial scan registers, choose feedback paths first.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Identifying partial scan opportunities n Construct register graph, which shows connections between registers: –nodes are registers; –edge between two nodes if there is a combinational path between them. n Sequential depth is distance from primary input to a node.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Register graph example machine register graph

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Analyzing register graphs n High sequential depth implies that the register is harder to test. n Registers contained register-graph cycles (FF2-FF3) are hard to test (although self- loops are not hard). n Add partial scan registers to effectively reduce sequential depth of node and its neighbors.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Built-in self test (BIST) n Includes on-chip machine responsible for: –generating tests; –evaluating correctness of tests. n Allows many tests to be applied. n Can’t afford large memory for test results - rely on compression and statistical analysis.

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR Generating vectors Use a linear-feedback shift register to generate a pseudo-random sequence of bit vectors:

Modern VLSI Design 2e: Chapter 8 Copyright  1998 Prentice Hall PTR BIST architecutre n One LFSR to generates test sequence. n Another LFSR captures/compresses results. n Can store a small number of signatures which contain expected compressed result for valid system.