1 IKI10230 Pengantar Organisasi Komputer Bab 7: Control Unit 28 Mei 2003 Bobby Nazief Qonita Shahab bahan kuliah: Sumber: 1. Hamacher. Computer Organization, ed Materi kuliah CS152/1997, UCB.

2 Pengendalian Eksekusi Instruksi: Hardwired Control

3 Prosesor: Control & Datapath Processor (active) Computer Control (“brain”) Datapath (“brawn”) Memory (passive) (where programs, data live when running) Devices Input Output

4 Review: Organisasi Prosesor (Single-bus) Y Z MDR MAR PC TEMP R(n-1) R0 IR Instruction Decoder ALU Carry-in Add Sub XOR Address lines Data lines Control lines Memory bus ALU control lines Control Unit Datapath Unit

5 Interaksi Control  Datapath STEPCONTROL SIGNALS 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.R3 out, MAR in, Read 5.R1 out, Y in, WMFC 6.MDR out, Add, Z in 7.Z out, R1 in, End Control Instruction Datapath IR Conditions Control Signals PC out MAR in ADD Ri in

6 Organisasi Unit Pengendali Decoder/ Encoder Control Step Counter Clock IR Status Flags Condition Codes CLK Control Signals             

7 Pemisahan Decoder & Encoder Encoder Control Step Counter Clock IR Status Flags Condition Codes Instruction Decoder Step Decoder LDI CLK    T 1 T 2    T n    Control Signals              LD INS n Run End Reset

8 Contoh Struktur Encoder untuk sinyal Z in °Fungsi Logika: Z in = T 1 + T 6  ADD + T 5  BR + … °Z in akan terjadi pada: T 1 : untuk setiap instruksi (instruksi berikut: PC+1) T 5 : untuk instruksi ADD T 6 : untuk instruksi BR ADD BR T5T5 T6T6 T1T1  Z in

9 Interaksi Memori  [Control,Datapath] Data Out Clk 5 RwRaRb Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

10 Pengendalian Eksekusi Instruksi: Microprogrammed Control

11 Microprogramming °Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance

12 Microinstructions STEPCONTROL SIGNALS 1.PC out, MAR in, Read, Clear Y, Carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.R3 out, MAR in, Read 5.R1 out, Y in, WMFC 6.MDR out, Add, Z in 7.Z out, R1 in, End IR in PC in PC out MAR in MDR out Y in R1 in R1 out R3 out Z in Z out Clear Y Carry-in Add Read WMFC End

13 Organisasi Microprogrammed Control Unit IR in PC in PC out MAR in MDR out Y in R1 in R1 out R3 out IR Starting Address Generator ClockμPC Control Store Control Word

14 Organisasi μProgrammed Control Unit: Branching IR Starting Address Generator ClockμPC Control Store Control Word Status Flags Condition Codes Addr.Microinstruction 0PC out, MAR in, Read, Clear Y, Carry-in to ALU, Add, Z in 1Z out, PC in, WMFC 2MDR out, IR in 3Branch to starting addr. of appropriate μroutine ……………………………………………………………………………. 25PC out, Y in, if N=0 then branch to μinstruction 0 26Offset-field-of-IR out, Add, Z in 27Z out, R1 in, End

15 Encoding of Microinstruction 0000: No transfer 0001: PC out 0010: MDR out 0011: Z out 0100: R0 out 0101: R1 out 000: No transfer 001: PC in 010: IR in 011: Z in 100: R0 in 101: R1 in 0000: ADD 0001: SUB. 1111: XOR 000: No transfer 001: MAR in 010: MDR in 011: TEMP in 100: Y in F4 F2 F1 F3 (4 bits) (3 bits) (4 bits) (3 bits) °Most signals are not needed simultaneously °Many are mutually exclusive: ALU: 1 function at a time Data source is unique °Organization: Vertical Organization (Highly Encoded μInstruction) Horizontal Organization (otherwise)

16 Microprogram Sequencing: Branching Implementation °1 Machine Instruction  1 Set of μInstructions large total number of μInstruction large Control Store °Many Addressing Modes  many instruction combinations results in many duplications of common parts °If the common parts are to be shared  many branches results in longer execution time  Need efficient branching techniqe  Bit-ORing

17 Microprogram Sequencing (1/2): Add src,R dst MAR  [PC]; Read; Z  [PC]+1 PC  [Z]; WMFC IR  [MDR] Branch[InstDec,OR] MAR  [PC]; Read; Z  [PC]+1 Z  [Rsrc] - 4 MAR  [PC]; Read; Z  [PC]+1 MAR  [Rsrc]; Read PC  [Z]; WMFC MAR, Rsrc  [Z]; Read Z  [Rsrc]Branch[171]; WMFC Start Indexed Autodecrement Autoincrement Register indirect

18 Microprogram Sequencing (2/2): Add src,R dst Branch[170,OR]; WMFC Branch[170,OR]; WMFC Branch[170,OR]; WMFC Branch[171]; WMFC End Indexed Autodecrement Autoincrement Register indirect MAR  [MDR]; Read; WMFC 170 Y  [MDR] 171 Z  [Y] + [Rdst] 172 Rdst  [Z] 173

19 Branching in Microinstruction: Add (R src )+,R dst R dst OP code R src Addr.Microinstruction 000PC out, MAR in, Read, Clear Y, Set carry-in, Add, Z in 001Z out, PC in, WMFC 002MDR out, IR in 003μBranch {μPC  101; μPC 5,4  [IR 10,9 ]; μPC 3  [IR 10 ].[IR 9 ].[IR 8 ]} 121Rsrc out, MAR in, Read, Clear Y, Set carry-in, Add, Z in 122Z out, Rsrc in 123μBranch {μPC  170; μPC 0  [IR 8 ]}, WMFC 170MDR out, MAR in, Read, WMFC 171MDR out, Y in 172Rdst out, Add, Z in 173Z out, Rdst in, End ADD IR 10,9 = 01 (autoincrement) IR 8 = 0 (direct) Mode Bit ORing

20 Microinstruction Sequencing: Organization μAR Control Store μIR Status Flags Condition Codes IR Decoding Circuits Next Address μ Instruction Decoder    Control Signals

21 Encoding of Microinstruction w/ Next Address 000: No transfer 001: PC out 010: MDR out 011: Z out 100: Rsrc out 101: Rdst out 000: No transfer 001: PC in 010: IR in 011: Z in 100: Rsrc in 101: Rdst in 0000: ADD 0001: SUB. 1111: XOR 000: No transfer 001: MAR in 010: MDR in 011: TEMP in 100: Y in F3 F1 F0 F2 (3 bits) (8 bits) (3 bits) Address of next microinstruction F4 F9 (1 bit)... (4 bits) F8 (1 bit) 0: NextAdrs 1: InstDec 0: No action 1: OR mode F10 (1 bit) 0: No action 1: OR indsrc

22 Content of μStore F0F1F2F3F4F5 F6F6 F7F7 F8F8 F9F9 F10F

23 /Etc

24 “Macroinstruction” Interpretation Main Memory execution unit control memory CPU ADD SUB AND DATA User program plus Data this can change! AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) one of these is mapped into one of these

25 Control: Hardware vs. Microprogrammed °Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial RepresentationFinite State Diagram Microprogram Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs Logic RepresentationLogic EquationsTruth Tables Implementation TechniquePLAROM “hardwired control”“microprogrammed control”