 HDLs – Verilog and Very High Speed Integrated Circuit (VHSIC) HDL  „ Widely used in logic design  „ Describe hardware  „ Document logic functions  „ Simulate logic before building  „ Synthesize code into gates

 HDL is a program that allows the user to implement complex functions  Digital systems are complex. Example: Processor  Designing a function with 10,000 gates in schematic is very difficult.  An HDL makes it easy by simply describing the function.  A tool can convert the described function in HDL into logic gates (Synthesis step in the design flow)

module half_added (Sum, Carry, A,B); input A, B; output Sum, Carry; wire Carry_bar; xor (Sum, A, B); //nand (Carry_bar, A, B); // not (Carry, Carry_bar); and (Carry, A, B); endmodule Declaration of Internal Signals Instantiation of Gates

module half_added (Sum, Carry, A,B); // Two slashes make a comment line //all commands are semi-colon delimited input A, B; output Sum, Carry; assign {Carry, Sum} = A+ B; endmodule  An assign statement is used for modeling only combinational logic and it is executed continuously.  Assign also called “Continuous assignment statement”

 Reg – that can store a value  Wire – that cannot store value, but connects two points. wire out; //”out” is a wire that only outputs reg out; //”out” is a register; it stores //also outputs a value reg [3:0] out_bus; // out_bus is a 4 bit register

Operator TypeOperator SymbolOperation Performed Arithmetic*Multiply /Division +Add -Subtract %Modulus Logical!Logical Negation (Not) &&Logical And ||Logical or Relational>Greater than <Less than >=Greater than or equal <=Less than equal Equality==Equality !=Inequality

Operator TypeOperator SymbolOperation Performed Reduction~Bitwise Negation ~&Nand |Or ~|Nor ^Xor ^~ / ~^Xnor Shift>>Right Shift <<Left Shift Concatenation{ }Concatenation Conditional?

 Every block with more than one statement must be included in begin and end. if (enable == 1) if (enable ==1) begin a=b; a=b; x=y; end case (state) 0: $display(“in state 0”); 1: begin a=b; $display(“in state 1 with multiple statements”); end default: $display(“default state”); endcase // Every case statement must end with endcase

 An initial block is executed only once when simulation starts (i.e. when time = 0).  Used in test benches.  If multiple initial blocks are declared, they all get executed at the beginning of simulation. initial begin a = 0; b = 0; end

 Always block executes always with a sensitive list associated with it.  A sensitive list is the one which tells the always block when to execute the block of code. (a or b) begin c = a & b; end  In the above example, symbol after the reserved keyword “always” indicates that the block will be triggered “at” the condition in parenthesis after

(a or b or sel) begin y = 0; if (sel == 0) begin y = a; end else begin y = b; end a b sel y 0 1

module Full_Adder (a, b, cin, sum, cout); input [3:0] a,b; input cin; output [3:0] sum; output cout; reg [3:0] sum; assign {cout, sum} = a+b+cin; endmodule

 Blocking Statements: A blocking statement must be executed before the execution of the statements that follow it in a sequential block. In the example below the first time statement to get executed is a = b followed by a=b b=c  Nonblocking Statements: Nonblocking statements allow you to schedule assignments without blocking the procedural flow. You can use the nonblocking procedural statement whenever you want to make several register assignments within the same time step without regard to order or dependence upon each other.

module example (); reg a,b,c,d; initial begin // Blocking Assignment a = #10 1’b1; //The simulator assigns 1 to time 10 b = #10 1’b1; //The simulator assigns 1 to time 20 end initial begin // Nonblocking Assignment c <= #10 1’b1; //The simulator assigns 1 to time 10 d <= #20 1’b0; //The simulator assigns 1 to time 20 end endmodule

Image From Asic-World

module DFF (clk, d, q); input clk, d; output q; reg q; (posedge clk) begin q <= d; end endmodule DFF d clk q

module DFF (clk, d, q); input clk, d; output q; reg q; (clk or d) begin q <= d; end endmodule

module DFF (clk, d, q); input clk, d; output q; reg q; wire a; (posedge clk) begin a <= d; q <= a; end endmodule DFF d clk a DFF q clk