FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Clocking disciplines Flip-flops. Latches.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Clocking disciplines n Rules for constructing sequential machines. –Combinations of registers and gates. –Behavior of clocks and primary inputs over time. n Rules are sufficient to guarantee that the system will work at some clock rate. –May not be as fast as we want.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Qualified clock n Clock logically combined with signal: DQ  sig1

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Flip-flop-based sequential machines

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Flip-flop rules Primary inputs change after clock (  ) edge. n Primary inputs must stabilize before next clock edge. n Rules allow changes to propagate through combinational logic for next cycle. n Flip-flop outputs hold current-state values for next-state computation.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Signals in flip-flop system positive clock edge

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Latch-based machines n Latches do not cut combinational logic when clock is active. n Latch-based machines must use multiple ranks of latches. n Multiple ranks require multiple phases of clock.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Two-sided latch constraint n Latch must be open less than the shortest combinational delay. n Period between latching operations must be longer than the longest combinational delay. n Note: difference between shortest and longest combinational delay may be large (sum 0 vs. sum 31 ).

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Latch shoot-through Latch may allow data to shoot through:

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Strict two-phase clocking discipline n Strict two-phase discipline is conservative but works. n Can be relaxed later with proper knowledge of constraints. n Strict two-phase machine makes latch-based machine behave more like flip-flop design, but requires multiple phases.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Strict two-phase architecture

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Two-phase clock Phases must not overlap: non-overlap region

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Why it works n Each phase has a one-sided constraint: phase must be long enough for all combinational delays. n If there are no combinational loops, phases can always be stretched to make that section of the machine work. n Total clock period depends on sum of phase periods.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Clocking types n Logic on different phases operate at different times—can’t mix signals from different phases. n Primary inputs must obey the same rules as internal signals. n Clocking types are bookkeeping that help us ensure that machine structure is valid.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Stable signals n A logic signal is always stable during one phase—phase in which the latch which produced it is not active. n Easiest to think of machine behavior in terms of stable signals, though signals propagate while not stable.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Signal types Clocks are separate type:  1,  2. n Two types of stable data signal: –stable  1 (s  1 ) –stable  2 (s  2 ) n A stable signal has a complementary valid signal: –stable  2 (s  2 ) = valid  1 (v  1 )

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Stable data signal inactive clock stable until latch feeding this logic goes active stable  2 becomes valid at end of  1

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR How clocking types combine

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Clocking types in the two-phase machine combinational logic DQ combinational logic DQ I 1 (s  2 ) 11 O 1 (s  2 ) I 2 (s  1 ) O 2 (s  1 ) s  1 s  2 22

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Clocking type propagation n Combinational logic does not change type of signal. n Primary inputs must be compatible. n Latches change signals from one clock type to another. n In strict system, never mix clocks with data signals in combinational logic.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Two-coloring combinational logic DQ combinational logic DQ I 1 (s  2 ) 11 O 1 (s  2 ) I 2 (s  1 ) O 2 (s  1 ) s  1 s  2 22

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Example: shift register n Want to displace bit by n registers in n cycles. n Each register requires two phases:

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Shift register operation  1 = 1,  2 = 0  1 = 0,  2 = 1

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Non-strict disciplines n Some relaxation of the rules can be useful: –reduce area; –increase performance. n Rules must be relaxed in a way that ensures the machine will still work.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Qualified clocks n Use logic to generate a clock signal which is not always active. n Qualification must not introduce glitches into the clock—glitches violate the fundamental definition of a clock by introducing extra edges. n Use stable signals to qualify clocks.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Uses of qualified clocks n May want to conditionally load a register. n May qualify a clock to turn off machine for low-power operation. n Latch must be not lose its value during inactive period. n Difficult to ensure that logic value will come high in time—use quasi-static latch.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Qualified clocks and skew n Logic in the clocking path introduces delay. n Delay can cause clock to arrive at latches at different times, violating clocking assumptions. n When designing qualification logic: –minimize and check skew; –sharpen clock edge.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Qualification skew example