1. 12006 MAPLD International ConferenceSpaceWire 101 Seminar Data Strobe (DS) Encoding Sam Stratton sam.stratton@aeroflex.com 2006 MAPLD International Conference Washington, D.C. September 25, 2006

2. 22006 MAPLD International ConferenceSpaceWire 101 Seminar Strobe signal is sent along with the serial Data The clock is extracted by XORing the Data and Strobe signals DS Encoding

3. 32006 MAPLD International ConferenceSpaceWire 101 Seminar Pros and Cons Pros Nearly 1 bit time of skew Margin Good Jitter Tolerance Cons Receiver data is asynchronous with respect to local clocks

4. 42006 MAPLD International ConferenceSpaceWire 101 Seminar Implementation Challenges Receiver for decode of Data Strobe waveforms is an asynchronous circuit Analyze asynchronous circuit to guarantee no race conditions violate timing Implementation of asynchronous circuits are difficult in FPGAs –FPGA vendors do not guarantee minimum timing of parts Routing variations for common circuit Interconnect delay variances –ASIC designs can more easily guarantee minimum timing of circuits

5. 52006 MAPLD International ConferenceSpaceWire 101 Seminar DS Circuit Analysis Only first 2 Flip Flips (FFs) are asynchronous –FF0 & FF1 All other FFs in shift register are synchronous with single clock edge Timing Checks –Setup Data changing –Hold Strobe changing –Minimum pulse width Conditions –Data changing –Strobe changing

6. 62006 MAPLD International ConferenceSpaceWire 101 Seminar Timing Checks Set-up Time Setup Checks –Ensure Data that generated the clock arrives before the clock Blue is faster than Red T (Data to FF[D]) < T (Data to FF[Clk]) - T (Set-up FF) For FPGA - use longest path and shortest path together for worst case –Consider rising and falling edge permutations FF0 DQ FF1 DQ DATA STROBE XOR CLK_BUFF I_3 DQ FF3 DQ DATA path delay DQ DQ XOR CLK_BUFF FF2 DQ DQ

7. 72006 MAPLD International ConferenceSpaceWire 101 Seminar Timing Checks Hold Time Hold Checks –Ensure Strobe generated clock does not latch the wrong Data Red shorter than Bit Period (T) of Data rate –Note Bit Period defined from rising to falling edge T Bit Period + T (Data to FF[D]) > T (Strobe to FF[Clk]) + T (Hold FF) For FPGA - use longest path and shortest path together for worst case –Consider rising and falling edge permutations FF0 DQ FF1 DQ DATA STROBE XOR CLK_BUFF I_3 DQ FF3 DQ DATA path delay DQ DQ XOR CLK_BUFF FF2 DQ DQ Data Strobe Clock Bit Period Longer Bit Period Shorter Bit Period skew

8. 82006 MAPLD International ConferenceSpaceWire 101 Seminar Timing Checks Minimum Edge Separation Min Edge Separation Checks Ensure Bit Period is greater than Absolute value of difference in Data clock generated path delay and Strobe clock generated path delay T Min Bit Period > | T (Strobe to FF[Clk]) - T (Data to FF[Clk]) | + T (Set-up) + T (Hold) For FPGA - use longest path and shortest path together for worst case –Consider rising and falling edge permutations FF0 DQ FF1 DQ DATA STROBE XOR CLK_BUFF I_3 DQ FF3 DQ DATA path delay DQ DQ XOR CLK_BUFF FF2 DQ DQ

9. 92006 MAPLD International ConferenceSpaceWire 101 Seminar ASIC vs FPGA Traces are the primary contributor to delays ASIC - Critical paths can be carefully managed FPGA - Path lengths cannot be changed, only links to paths FPGA, Fixed Architecture ASIC, No Fixed Architecture

10. 102006 MAPLD International ConferenceSpaceWire 101 Seminar Summary DS Encoding offers good Skew and jitter margins Better suited for ASIC Implementations FPGA Implementations can be facilitated by –offloading the critical timing to an external device –doing worst case timing analysis use longest and shortest paths together