Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 4, 2011 Synchronous Circuits
Today Clocking –Latches –Registers Timing discipline Penn ESE370 Fall DeHon 2
Clocking Latches, Registers Penn ESE370 Fall DeHon 3
Why Clocked Circuits? Synchronize external events Reuse logic –FSM –Pipelining Synchronize internal use of logic Penn ESE370 Fall DeHon 4
Challenge Logic paths have different delays –E.g. different output bits in an adder Delay of signal data dependent –E.g. length of carry Delay is chip dependent –E.g. Threshold Variation Delay is environment dependent –E.g. Temperature Penn ESE370 Fall DeHon 5
Challenge Logic paths have different delays Delay of signal data dependent Delay is chip dependent Delay is environment dependent Proper behavior depends on inputs being coordinated –Match the inputs that should interact Penn ESE370 Fall DeHon 6
Discipline Add circuit elements to –hold values –and change at coordinated point Control when changes seen by circuit Only have to make sure to wait long enough for all results Decouple –timing of signal change –from timing of signal usage Penn ESE370 Fall DeHon 7
Synchronous Discipline Add state elements (registers, latches) Compute –From state elements –Through combinational logic –To new values for state elements Penn ESE370 Fall DeHon 8
What does this do? Penn ESE370 Fall DeHon 9
Latch =0 Out=In =1 Out=Out transitions 0 1 Out holds value Penn ESE370 Fall DeHon 10
Latch In pass-through mode ( =0), –acts like buffer In latch mode ( =1), –holds last value given Penn ESE370 Fall DeHon 11
Latch In pass-through mode ( =0), –acts like buffer In latch mode ( =1), –holds last value given Timing Requirements? Penn ESE370 Fall DeHon 12
Latch Timing Must present input value sufficiently before the transitions 0 1 –Must have time to propagate and charge Out –About how long is that in this case? Setup Time (t su ) – must setup latch input prior to pass hold transition Penn ESE370 Fall DeHon 13
Latch Timing Must not change input before switched over to hold state –How long in this case? –Takes time for inverter to charge before hold path enabled. Penn ESE370 Fall DeHon 14
Latch Timing Must not change input before switched over to hold state Hold Time (t hold )– must hold data input until pass hold transition complete Penn ESE370 Fall DeHon 15
What happens here? Penn ESE370 Fall DeHon 16
Observe Latch alone –In flow-through mode half of cycle –Can still get flow-through, combinational cycles Penn ESE370 Fall DeHon 17
Multiple Latch Discipline Open latches at disjoint times At all times one latch on every path is closed Penn ESE370 Fall DeHon 18
Register Two back-to-back latches –Open one latch at a time –Having one of each on every cycle breaks up combinational cycle Penn ESE370 Fall DeHon 19
Register Pass hold on input latch samples value Hold pass on output latch presents stored value to circuit Penn ESE370 Fall DeHon 20 Master and Slave latches
Register How long from 0 rise to output? How long from 1 fall to output –Part of clk output (t clk-q ) Penn ESE370 Fall DeHon 21
Clock Signal Can we use a single signal for clock? Penn ESE370 Fall DeHon 22
Clock Issues Possible failure modes? –Flow through during transition? –Loading on clock phases –Delay in compute 1 ? Penn ESE370 Fall DeHon 23
What if it’s early? 0 early Penn ESE370 Fall DeHon 24
What if it’s late? 0 late Penn ESE370 Fall DeHon 25
What does this do? Penn ESE370 Fall DeHon 26
What does this do? Outputs when –Input 0? –Input 1? Can ever both be on? What does output waveform look like? Penn ESE370 Fall DeHon 27
Clocking Discipline Penn ESE370 Fall DeHon 28 Identify: setup, hold, clk->Q, logic evaluation
Clocking Discipline Penn ESE370 Fall DeHon 29
Clocking Discipline Follow discipline of combinational logic broken by registers Compute –From state elements –Through combinational logic –To new values for state elements As long as clock cycle long enough, –Will get correct behavior Penn ESE370 Fall DeHon 30
Next Week Monday: guest lecturer (andre away) Tuesday: Andre away (no office hour) Wednesday: Midterm –No lecture –Midterm 7-9pm in Towne 303 –New Project out Thursday: (read project) Friday: Class Penn ESE370 Fall DeHon 31
Ideas Synchronize circuits –to external events –disciplined reuse of circuitry Leads to clocked circuit discipline –Uses state holding element –Prevents Combinational loops Timing assumptions (More) complex reasoning about all possible timings Penn ESE370 Fall DeHon 32