Paper Discussion Reim Doumat & Thomas Watteyne « Simulation of Soc Architectures »

« Overview of the Ptolemy Project » Jul « Modeling and Simulation Issues of Programmable Architectures » Mar « Rapid System-Level Performance Evaluation and Optimization for Application Mapping onto SoC Architecures » Oct « Modeling and Simultaion of Embedded Processors Using Abstract State Machine » Mar. 2001

3 Introduction to Modeling, Design and Simulation General Overview “Modeling and Simulation of Embedded Processors Using Abstract State Machines” “Rapid System-Level Performance Evaluation and Optimization for Application Mapping onto SoC Architectures”

Part I Introduction to Modeling, Design and Simulation

5 Overview I. Introduction II. Machine and Hardware Description Languages, the LISA example III. Models of computation, the Ptolemy example

6 Introduction Push-pull effect Definitions MDL, HDL Computation Models The push-pull effect System complexity New applications Semiconductor technology Time-to-market !! Designer productivity

7 The push-pull effect productivity re-usability flexibility In embedded system design  Effective design phase Introduction Push-pull effect Definitions MDL, HDL Computation Models

8 Definitions Modeling : representing an architecture (mathematical model, constructive model) Design : defining an architecture Simulation : executable model Introduction Push-pull effect Definitions MDL, HDL Computation Models

9 Introduction MDL, HDL Why LISA ? Overview LISA Validation Computation Models Why LISA ? Language for Instruction Set Architecture Electronic systems Programmable Architecture ASIC, DSP… processors Code generation and simulation tools : simulator assembler linker graphical debugger

10 Programmable Architecture overview Hardware (processor) Operating System User Application ex: POSIX Instruction Set Hardware Description Langage (ex : VHDL, Verilog) Machine Description Language (ex : LISA) Introduction MDL, HDL Why LISA ? Overview LISA Validation Computation Models

11 LISA LISA processor description processor model debuggersimulatorSimulator compilerassemblerlinker Generic Processor model Software developpement environment Introduction MDL, HDL Why LISA ? Overview LISA Validation Computation Models

12 Validation simulation speed simulation speed (x1000 instruction/cycles per second) Use of compilation simulation LISA  VHDL ? assembler/linker speed equivalent Introduction MDL, HDL Why LISA ? Overview LISA Validation Computation Models

13 Introduction MDL, HDL Computation Models « Overview of the Ptolemy Project » Jul Computation Models

14 Ptolemy II - Introduction Gabriel (1986–1991) Ptolemy Classic (1990–1997) Ptolemy II (1996–to date) ? Introduces: - Domain polymorphism - Modal Models Introduction MDL, HDL Computation Models Introduction Ptolemy Project Models Choosing Facts

15 Definition: Definition: The project studies - modeling, - simulation, - design of concurrent, real-time, embedded systems Characteristics: - Components built on top of Java compiler (Soot) - XML as data representation - Concept of migrating models Ptolemy - Introduction Introduction MDL, HDL Computation Models Introduction Ptolemy Project Models Choosing Facts

16 Complete separation of the abstract synthax from the semantics. Synthax Synthax, Actor-Oriented design : - models, actors, ports, parameters, channels - represented graphically, XML or by program with specific API Semantics Semantics, the “physical laws” : - models constructed under model of computation - choice of model of computation has deep impact on implementation - interoperability of executable models - hierarchical mix of domains Ptolemy Project Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts

17 Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts Example of the actor oriented design

18 Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts Ptolemy II- Modeling and Design

19 Ptolemy – Modeling & Design Focus on: - Embedded software - Actor oriented design (Version 4.0.1) - Architecture Design 1) Components designed to be domain polymorphic 2) Interaction mechanisms among domains 3) Development of a meta-model describing models of computation Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts

20 Models of Computation At least 12 different models of computation Variety of models because : time (continuous, discrete, causal) concurency, interactions different underlying mathematical models Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts

21 Component Interaction (Demand-Driven, e.g. Web Browsers) Communication Sequential Processes (use of rendez-vous) Continuous Time Discrete-Events Distributed Discrete Events Discrete Time Finite-State Machines Process Networks Synchronous Dataflow Giotto (hard real time) Synchronous/reactive Timed Multitasking Models of Computation Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts

22 Choosing a Model of Computation Most designer faced to only one or two Choice is very important (time, event, etc.) Unifying not possible... (complex) Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts

23 Core packages: support data model and actor model User Interface packages: support XML file format (MoML) Library packages: define actors to be domain polymorphic domains : subpackages of ptolemy domains package Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts Ptolemy II –What’s the Architecture?

24 Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts Ptolemy II – some capabilities Higher level concurrent design in Java Better modularization through the use of packages Complete separation of the abstract syntax from the semantics Domain-polymorphic actors

25 Ptolemy in facts 3 rd generation : Ptolemy II Java as a programming language Visual synthax Set of packages Introduction MDL, HDL Computation Models Introduction Ptolemy Models Choosing Facts

Part II “Rapid System-Level Performance Evaluation and Optimization for Application Mapping onto SoC Architectures” October 2002 Sumit Mohanty, Viktor K. Prasanna

27 Introduction GenM HiPerE MILAN Evaluation& optimization of performance During application design Estimation at the system level Estimation of specific component performance Introduction GenM HiPerE MILAN conclusion

28 Introduction GenM HiPerE MILAN conclusion Generic Model for Application Mapping onto SoC Architecture Components of the GenM Model DVS (Dynamic Voltage Scaling)

29 Introduction GenM HiPerE MILAN conclusion Why to use GenM? Rapid estimation of performance. Development of efficient application designs (High Level abstraction). Development of optimization techniques for mapping application onto SoC architecture.

30 Introduction GenM HiPerE MILAN conclusion -system-level performance estimation HiPerE (High-Level Performance Estimator) HiPerE GenM (Target SoC architecture) Performance parameters Application Task Graph Estimation of System- level energy & latency Activity Report for Each component in the target architecture -Interpretive simulator

31 Component specific Performance Estimation using MILAN Component Specific Performance Estimation MILAN(Model based Integrated simuLAtioN Application Model Resource Model Program Implementing The Task Low-level simulator Component Specific Estimates Feedback Source code Configure Update Energy And Latency Estimates Introduction GenM HiPerE MILAN conclusion

32 Introduction GenM HiPerE MILAN conclusion Performance estimation includes? Cost for execution Data access Memory activation reconfiguration

33 Application Optimization Using MILAN Hierarchical Simulation for DES in MILAN Introduction GenM HiPerE MILAN conclusion

34 Application Optimization Using MILAN Introduction GenM HiPerE MILAN conclusion

35 Introduction GenM HiPerE MILAN conclusion Conclusion By using (GenM,HiPerE,MILAN) solve these problems: Estimation of system-level performance for SoC architectures. Lack of high-level abstraction for SoC architectures. Lack of standard interface between different component simulators.

Part III “Modeling and Simulation of Embedded Processors Using Abstract State Machines” March 2001 Dirk Fischer, Jurgën Teich, Ralph Weper

37 Overview I. Architecture/compiler co-design II. Abstract State Machines III. The BUILDABONG project IV. Paper’s Interest

I. Architecture/Compiler co-design in ASIPs

39 The needs “ - ASIP ASAP ? ” Application Specific Instruction Set Processors As soon as possible ASIPASAP customized processors special applications (signal processing…) time to market optimal application/processor tradeoff co-design Needs Process Related work ASMs BUILDABONG Interest

40 Process Simple instruction set Complex application complex instruction set simple application More computation time, more memory More design / manufacturing process costs Application Processor Exploration Simulation Architecture/compile r co-design co-design Needs Process Related work ASMs BUILDABONG Interest

41 work on architecture/compiler co-design LISA University of Aachen, Germany Compiled simulator  100K instructions per second CASTEL VHDL RTL DATA PATH MODEL extended FSM EXPRESSION University of California, USA V-SAT Graphical Design Environment EXPRESSION model Retargetable compiler Cycle accurate simulator co-design Needs Process Related work ASMs BUILDABONG Interest

II. Abstract State Machines

43 The Mathematics co-design ASMs Mathematics Modeling Advantages BUILDABONG Interest universe Functions Relations == ? < ? == ? >= ? == ? > ? <= ? structure  Algebra

44 The Mathematics co-design ASMs Mathematics Modeling Advantages BUILDABONG Interest Μ = (V, f 1, f 2, …, f n ) Finite vocabulary Finite set of n-ary functions over V (State of M ≡ algebra over V ) Abstract State Machine S 0 P Initial state S 0 + set of transition rules P = ASM

45 The Mathematics co-design ASMs Mathematics Modeling Advantages BUILDABONG Interest Transition Rule If then endif Update rule f(t1, t 2, …, t n ) := t No relations  boolean value

46 The Mathematics co-design ASMs Mathematics Modeling Advantages BUILDABONG Interest Operationnal semantics SiSi S i+2 SnSn R state Update rule S i+1 R R Terminal state No cycling…

47 Modeling processors with ASMs co-design ASMs Mathematics Modeling Advantages BUILDABONG Interest cycle accurate model, register transfer level a register tranfer is conditionned (mode registers, instruction bits) “guarded register transfer paterns” (Leupers) If then endif  ASMs

48 Advantages co-design ASMs Mathematics Modeling Advantages BUILDABONG Interest short description (ARM7, 200 lines XASM) readability cycle accuracy simulation speed (?) XASM environment supports C-libraries (irregular arithmetic operations on arbitrary large word-lengths) “natural” mathematical tool

III. The BUILDABONG project

50 General View ASM Simulator Generator (Gem-Mex) Simulator Retargetable Compiler Parser Linker Loader ArchitectureComposer ASM Generator Assembler Program library Instruction Set Description ANSI C Program Explorer Graphical input co-design ASMs BUILDABONG General view Editor XASM Simulator Future work Interest

51 Graphical Architecture Editor co-design ASMs BUILDABONG General view Editor XASM Simulator Future work Interest libraries hierarchical

52 XASM-code generation co-design ASMs BUILDABONG General view Editor XASM Simulator Future work Interest

53 XASM-code generation Library include co-design ASMs BUILDABONG General view Editor XASM Simulator Future work Interest

54 XASM-code generation Function declaration co-design ASMs BUILDABONG General view Editor XASM Simulator Future work Interest

55 XASM-code generation Sequential element initialization co-design ASMs BUILDABONG General view Editor XASM Simulator Future work Interest

56 XASM-code generation Guarded update rules (memory and registers) ? co-design ASMs BUILDABONG General view Editor XASM Simulator Future work Interest

57 Automatic Simulator Generator co-design ASMs BUILDABONG General view Editor XASM Simulator Future work Interest ?

58 To-Do list… co-design ASMs BUILDABONG General view Editor XASM Simulator Future work Interest ASM Simulator Generator (Gem-Mex) Simulator Retargetable Compiler Parser Linker Loader ArchitectureComposer ASM Generator Assembler Program library Instruction Set Description ANSI C Program Explorer Graphical input

IV. The paper’s interest

60 Criticism co-design ASMs BUILDABONG Interest meets the demand structured project « natural » modeling tool but proprietary graphical language openings Fine-tuning of the compiler (different needs) Conversion tools with HDLs