Sistemi Elettronici Programmabili13-1 MULTI OSC + CLOCK FILTER LVD POWER SUPPLY CONTROL 8 BIT CORE ALU PROGRAM MEMORY RAM I2CI2C PORT A SPI PORT B 16-BIT TIMER A PORT C 8-BIT ADC 16-BIT TIMER B WATCHDOG INTERNAL CLOCK ADDRESS AND DATA BUS OSC1 OSC2 VDD VSS nRESET PA7..0 (8 bits) PB7..0 (8 bits) PC5..0 (6 bits) ST7: Block Diagram

Sistemi Elettronici Programmabili13-2 ST Package

Sistemi Elettronici Programmabili13-3 ST72254 Memory Map

Sistemi Elettronici Programmabili13-4 ST72254 – Interrupt Vector

Sistemi Elettronici Programmabili13-5 ST72254 Registers (1)

Sistemi Elettronici Programmabili13-6 ST72254 Registers (2)

Sistemi Elettronici Programmabili13-7 ST72254 Registers (IO)

Sistemi Elettronici Programmabili13-8 ST72254 Registers (Timer)

Sistemi Elettronici Programmabili13-9 ST72254 Registers (ADC)

Sistemi Elettronici Programmabili13-10 IO Port: Block Diagram

Sistemi Elettronici Programmabili13-11 IO Port Configurations - Input

Sistemi Elettronici Programmabili13-12 IO Port Configurations – Output Opendrain

Sistemi Elettronici Programmabili13-13 IO Port Configurations – Output Push Pull

Sistemi Elettronici Programmabili13-14 IO Port: Registers

Sistemi Elettronici Programmabili13-15 ADC: Overview (1) 8-BIT SUCCESSIVE APPROXIMATIONS CONVERTER WITH UP TO 8 ANALOG CHANNELS FEATURE : –Accuracy : 1 LSB –Total Unajusted Error MAX : 1 LSB –Conversion time : 24 CPU cycle ie 3µs at full speed (8MHz) FLAGS –COCO : end of conversion (Status flag) –ADON : ADC on/off bit (to reduce power consumption)

Sistemi Elettronici Programmabili13-16 ADC: Overview (2) LOW CONSUMPTION MODES –Wait mode doesn't affect the ADC –Halt mode stops the ADC. HARDWARE –ST72334 and ST725xx : Vdda and Vssa must be connected externally respectivelly to Vdd and Vss through decoupling capacitors. –ST72254 : connection done internally RATIOMETRIC In the Functionnal Range –If analog voltage input > Vdd : converted result = FFh (no overflow indication) –If analog voltage input < Vss : converted result = 00h (no underflow indication)

Sistemi Elettronici Programmabili13-17 ADC: Block Diagram

Sistemi Elettronici Programmabili13-18 ADC: Registers

Sistemi Elettronici Programmabili13-19 Timer: Block Diagram

Sistemi Elettronici Programmabili13-20 Timer: Block Diagram (H)

Sistemi Elettronici Programmabili13-21 Timer: Block Diagram (L)

Sistemi Elettronici Programmabili13-22 Timer: Read Sequence

Sistemi Elettronici Programmabili13-23 Timer: Input Capture

Sistemi Elettronici Programmabili13-24 Timer: Output Compare

Sistemi Elettronici Programmabili13-25 TIMER: PWM Mode Automatic generation of a Pulse Width Modulated signal Period &pulse lenght set by software: –The first Output Compare Register OC1R contains the length of the pulse –The second Output Compare Register OCR2 contains the period of the pulse Resolution up to 100 steps at 20 KHz (fCPU =4 MHz): 1% of accuracy on the duty cycle t T

Sistemi Elettronici Programmabili13-26 Timer: PWM Flow When the free running counter reaches OC2R register value When the free running counter reaches OC1R register value l Free running counter is initialized to FFFCh l OLVL2 bit level is applied on the OCMP1 pin l ICF1 bit is set l OLVL1 bit level is applied on the OCMP1 pin

Sistemi Elettronici Programmabili13-27 Timer: PWM Counter OCMP1 Ouput Compare pin Timer output FFFFh Compare h Compare 2 FFFCh Ttimer × Tmax = OLVL1=0 OLVL2= 1 FREE RUNNING COUNTER VALUE time

Sistemi Elettronici Programmabili13-28 Timer: CR1

Sistemi Elettronici Programmabili13-29 Timer: CR2

Sistemi Elettronici Programmabili13-30 Timer: SR

Sistemi Elettronici Programmabili13-31 Schmitt Trigger: Caratteristica Inverter Sistemi Elettronici Programmabili13-31 t t Vin Vout

Sistemi Elettronici Programmabili13-32 Schmitt Trigger: Caratteristica Vin Vout

Sistemi Elettronici Programmabili13-33 Schmitt Trigger: Inverter - Commutazioni Spurie t t Vin Vout

Sistemi Elettronici Programmabili13-34 Schmitt Trigger: Commutazione t t Vin Vout