1. 1 Analog-to-Digital Converter (ADC)

2. 2 ADC Features (1/3) ADC conversion rate 1 MHz and 12-bit resolution – 1µs conversion time at 56 MHz – 1.17µs conversion time at 72 MHz Conversion range: 0 to 3.6 V ADC supply requirement: 2.4V to 3.6 V ADC input range: VREF- ≤ VIN ≤ VREF+ (VREF+ and VREF- available only in LQFP100 package) Dual mode (on devices with 2 ADCs): 8 conversion mode Up to 18 multiplexed channels: – 16 external channels – 2 internal channels: connected to Temperature sensor and internal reference voltage (VREFINT = 1.2V)

3. 3 ADC Features (2/3) Channels conversion groups: –Up to 16 channels regular group –Up to 4 channels injected group Single and continuous conversion modes Sequencer-based scan mode for up to 16 conversion External trigger option for both regular and injected conversion Channel by channel programmable sampling time Discontinuous mode on regular and injected groups Self-calibration

4. 4 ADC Features (3/3) Left or right Data alignment with inbuilt data coherency Analog Watchdog on high and low thresholds Interrupt generation on: –End of Conversion –End of Injected conversion –Analog watchdog DMA capability (only on ADC1)

5. 5 ADC Block Diagram

6. 6 ADC Regular channels group Programmable number of regular channels: Up to 16 channels Programmable sample time and conversion sequence Conversion started by: –Software through start bit –External trigger generated by: Timer1 CC1 Timer1 CC2 Timer1 CC3 Timer2 CC2 Timer3 TRGO Timer4 CC4 EXTI Line11

7. 7 ADC Injected channels group Programmable number of injected channels: Up to 4 channels Programmable sample time and conversion sequence Conversion started by: – JAUTO: automatic injected conversion after regular channels conversion – Software through start bit – External trigger generated by: Timer1 TRGO Timer1 CC4 Timer2 TRGO Timer2 CC1 Timer3 CC4 Timer4 TRGO EXTI Line15

8. 8 Analog sample time ADCCLK, up to 14MHz, taken from PCLK2 through a prescaler (Div2, Div4, Div6 and Div8) Three bits programmable sample time cycles for each channel: –1.5 cycles –7.5 cycles –13.5 cycles –28.5 cycles –41.5 cycles –55.5 cycles –71.5 cycles –239.5 cycles ADC ADCCLK ADC Prescalers: Div2, Div4, Div6 and Div8 PCLK2 55.5 cycles 7.5 cycles 71.5 cycles 41.5 cycles 13.5 cycles 28.5 cycles 1.5 cycles 239.5 cycles Sample Time Selection SMPx[2:0]

9. 9 Sequencer Sequencer: different order, different sampling time and oversampling possibility. Example: - Conversion of channels: 1, 2, 8, 4, 7, 3 and 11 - Different sampling time. - Oversampling of channel 7. Channel1Channel2Channel8Channel4Channel7 Channel3Channel11 13.5 cycles28.5 cycles 7.5 cycles 1.5 cycles 71.5 cycles

10. 10 ADC conversion modes Four conversion mode are available: CHx Start Stop CHx Start Stop...... CHn CHx Start CHx Start...... CHn Single channel single conversion mode Multi-channels (Scan) single conversion mode Multi-channels (Scan) continuous conversion mode Single channel continuous conversion mode

11. 11 ADC Analog Watchdogs 12-bit programmable analog watchdog low and high thresholds Enabled on one, some or all converted channels: one regular or/and injected channel, all injected or/and regular channels. Interrupt generation on low or high thresholds detection Status Register Analog Watchdog Low Threshold Temp Sensor V REFINT ADC_IN0 ADC_IN1 ADC_IN15...... AWD High Threshold

12. 12 ADC dual modes Available in devices with two ADCs: ADC1 master and ADC2 slave ADC1 and ADC2 triggers are synchronized internally for regular and injected channels conversion GPIO Ports Temp Sensor V REFINT Up to 4 injected channels Up to 16 regular channels ADC_IN0 ANALOG MUX … ADC_IN1ADC_IN15 ADC1 Analog ADC2 Analog Digital MasterDigital Slave External event synchronization External event (Regular group) External event (Injected group) Data register EOC/JEOC …

13. 13 Now you are able to… Develop your application around STM32F10x device

14. 14 Thank You !